@@ -2299,24 +2299,24 @@ define i32 @test_allocsize(i64 %len, i1* %test_base) nofree nosync {
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; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 [[TMP12]]
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; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 0
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; CHECK-NEXT: [[TMP69:%.*]] = bitcast i32* [[TMP68]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD :%.*]] = load <4 x i32>, <4 x i32>* [[TMP69]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP69]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 4
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; CHECK-NEXT: [[TMP71:%.*]] = bitcast i32* [[TMP70]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD4 :%.*]] = load <4 x i32>, <4 x i32>* [[TMP71]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD4 :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP71]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 8
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; CHECK-NEXT: [[TMP73:%.*]] = bitcast i32* [[TMP72]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD5 :%.*]] = load <4 x i32>, <4 x i32>* [[TMP73]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD5 :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP73]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 12
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; CHECK-NEXT: [[TMP75:%.*]] = bitcast i32* [[TMP74]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD6 :%.*]] = load <4 x i32>, <4 x i32>* [[TMP75]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD6 :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP75]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP76:%.*]] = xor <4 x i1> [[TMP39]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[TMP77:%.*]] = xor <4 x i1> [[TMP47]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[TMP78:%.*]] = xor <4 x i1> [[TMP55]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[TMP79:%.*]] = xor <4 x i1> [[TMP63]], <i1 true, i1 true, i1 true, i1 true>
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- ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_LOAD ]], <4 x i32> zeroinitializer
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- ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_LOAD4 ]], <4 x i32> zeroinitializer
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- ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_LOAD5 ]], <4 x i32> zeroinitializer
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- ; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_LOAD6 ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4 ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5 ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6 ]], <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP80]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]]
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; CHECK-NEXT: [[TMP81]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]]
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; CHECK-NEXT: [[TMP82]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]]
@@ -2467,24 +2467,24 @@ define i32 @test_allocsize_array(i64 %len, i1* %test_base) nofree nosync {
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; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 [[TMP12]]
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; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 0
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; CHECK-NEXT: [[TMP69:%.*]] = bitcast i32* [[TMP68]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD :%.*]] = load <4 x i32>, <4 x i32>* [[TMP69]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP69]], i32 4, <4 x i1> [[TMP39]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 4
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; CHECK-NEXT: [[TMP71:%.*]] = bitcast i32* [[TMP70]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD4 :%.*]] = load <4 x i32>, <4 x i32>* [[TMP71]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD4 :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP71]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 8
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; CHECK-NEXT: [[TMP73:%.*]] = bitcast i32* [[TMP72]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD5 :%.*]] = load <4 x i32>, <4 x i32>* [[TMP73]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD5 :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP73]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 12
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; CHECK-NEXT: [[TMP75:%.*]] = bitcast i32* [[TMP74]] to <4 x i32>*
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- ; CHECK-NEXT: [[WIDE_LOAD6 :%.*]] = load <4 x i32>, <4 x i32>* [[TMP75]], align 4
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+ ; CHECK-NEXT: [[WIDE_MASKED_LOAD6 :%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32( <4 x i32>* [[TMP75]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP76:%.*]] = xor <4 x i1> [[TMP39]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[TMP77:%.*]] = xor <4 x i1> [[TMP47]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[TMP78:%.*]] = xor <4 x i1> [[TMP55]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[TMP79:%.*]] = xor <4 x i1> [[TMP63]], <i1 true, i1 true, i1 true, i1 true>
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- ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_LOAD ]], <4 x i32> zeroinitializer
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- ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_LOAD4 ]], <4 x i32> zeroinitializer
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- ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_LOAD5 ]], <4 x i32> zeroinitializer
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- ; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_LOAD6 ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4 ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5 ]], <4 x i32> zeroinitializer
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+ ; CHECK-NEXT: [[PREDPHI9:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[WIDE_MASKED_LOAD6 ]], <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP80]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]]
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; CHECK-NEXT: [[TMP81]] = add <4 x i32> [[VEC_PHI1]], [[PREDPHI7]]
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; CHECK-NEXT: [[TMP82]] = add <4 x i32> [[VEC_PHI2]], [[PREDPHI8]]
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