0051-RISCV-Codegen-support-for-FPR32-stack-loads-stores.patch

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@lowrisc.org>
Subject: [RISCV] Codegen support for FPR32<->stack loads/stores

---
 lib/Target/RISCV/RISCVInstrInfo.cpp | 34 ++++++++++++++---------
 test/CodeGen/RISCV/float-mem.ll     | 55 +++++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+), 13 deletions(-)

diff --git a/lib/Target/RISCV/RISCVInstrInfo.cpp b/lib/Target/RISCV/RISCVInstrInfo.cpp
index e2fc3ad91e0..b630fb87286 100644
--- a/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -54,15 +54,19 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
-    unsigned Opcode = Subtarget.is64Bit() ? RISCV::SD : RISCV::SW;
-    BuildMI(MBB, I, DL, get(Opcode))
-        .addReg(SrcReg, getKillRegState(IsKill))
-        .addFrameIndex(FI)
-        .addImm(0);
-  } else {
+  unsigned Opcode;
+
+  if (RISCV::GPRRegClass.hasSubClassEq(RC))
+    Opcode = Subtarget.is64Bit() ? RISCV::SD : RISCV::SW;
+  else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
+    Opcode = RISCV::FSW;
+  else
     llvm_unreachable("Can't store this register to stack slot");
-  }
+
+  BuildMI(MBB, I, DL, get(Opcode))
+      .addReg(SrcReg, getKillRegState(IsKill))
+      .addFrameIndex(FI)
+      .addImm(0);
 }
 
 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -74,12 +78,16 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
-    unsigned Opcode = Subtarget.is64Bit() ? RISCV::LD : RISCV::LW;
-    BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
-  } else {
+  unsigned Opcode;
+
+  if (RISCV::GPRRegClass.hasSubClassEq(RC))
+    Opcode = Subtarget.is64Bit() ? RISCV::LD : RISCV::LW;
+  else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
+    Opcode = RISCV::FLW;
+  else
     llvm_unreachable("Can't load this register from stack slot");
-  }
+
+  BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
 }
 
 void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
diff --git a/test/CodeGen/RISCV/float-mem.ll b/test/CodeGen/RISCV/float-mem.ll
index f1cbb4330f3..0f543ef083f 100644
--- a/test/CodeGen/RISCV/float-mem.ll
+++ b/test/CodeGen/RISCV/float-mem.ll
@@ -82,3 +82,58 @@ define float @flw_fsw_constant(float %a) nounwind {
   store float %3, float* %1
   ret float %3
 }
+
+declare void @notdead(i8*)
+
+define float @flw_stack(float %a) nounwind {
+; Tests RISCV::LdFPR32_FI
+; RV32IF-LABEL: flw_stack:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    sw s1, 8(sp)
+; RV32IF-NEXT:    addi s1, a0, 0
+; RV32IF-NEXT:    lui a0, %hi(notdead)
+; RV32IF-NEXT:    addi a1, a0, %lo(notdead)
+; RV32IF-NEXT:    addi a0, sp, 4
+; RV32IF-NEXT:    jalr ra, a1, 0
+; RV32IF-NEXT:    fmv.w.x ft0, s1
+; RV32IF-NEXT:    flw ft1, 4(sp)
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    lw s1, 8(sp)
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    jalr zero, ra, 0
+  %1 = alloca float, align 4
+  %2 = bitcast float* %1 to i8*
+  call void @notdead(i8* %2)
+  %3 = load float, float* %1
+  %4 = fadd float %3, %a ; force load in to FPR32
+  ret float %4
+}
+
+define void @fsw_stack(float %a, float %b) nounwind {
+; Tests RISCV::StFPR32_FI
+; RV32IF-LABEL: fsw_stack:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fsw ft0, 8(sp)
+; RV32IF-NEXT:    lui a0, %hi(notdead)
+; RV32IF-NEXT:    addi a1, a0, %lo(notdead)
+; RV32IF-NEXT:    addi a0, sp, 8
+; RV32IF-NEXT:    jalr ra, a1, 0
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    jalr zero, ra, 0
+  %1 = fadd float %a, %b ; force store from FPR32
+  %2 = alloca float, align 4
+  store float %1, float* %2
+  %3 = bitcast float* %2 to i8*
+  call void @notdead(i8* %3)
+  ret void
+}
-- 
2.16.2