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[RISCV] Lower vfmv.s.f intrinsics to VFMV_S_F_VL first
Currently vfmv.s.f intrinsics are directly selected to their pseudos via a tablegen pattern in RISCVInstrInfoVPseudos.td, whereas the other move instructions (vmv.s.x/vmv.v.x/vmv.v.f etc.) first get lowered to their corresponding VL SDNode, then get selected from a pattern in RISCVInstrInfoVVLPatterns.td This patch brings vfmv.s.f inline with the other move instructions, and shows how the LMUL reducing combine for VFMV_S_F_VL and VMV_S_X_VL results in the discrepancy in the test added in llvm#75544. Split out from llvm#71501, where we did this to preserve the behaviour of selecting vmv_s_x for VFMV_S_F_VL for small enough immediates.
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+23
-45
lines changed

4 files changed

+23
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lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -8500,6 +8500,9 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
85008500
return DAG.getNode(RISCVISD::VMERGE_VL, DL, VT, SelectCond, SplattedVal,
85018501
Vec, DAG.getUNDEF(VT), VL);
85028502
}
8503+
case Intrinsic::riscv_vfmv_s_f:
8504+
return DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, Op.getSimpleValueType(),
8505+
Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
85038506
// EGS * EEW >= 128 bits
85048507
case Intrinsic::riscv_vaesdf_vv:
85058508
case Intrinsic::riscv_vaesdf_vs:

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

-26
Original file line numberDiff line numberDiff line change
@@ -7415,32 +7415,6 @@ foreach vti = AllIntegerVectors in {
74157415
// vmv.s.x is handled with a custom node in RISCVInstrInfoVVLPatterns.td
74167416
}
74177417

7418-
//===----------------------------------------------------------------------===//
7419-
// 16.2. Floating-Point Scalar Move Instructions
7420-
//===----------------------------------------------------------------------===//
7421-
7422-
foreach fvti = AllFloatVectors in {
7423-
let Predicates = GetVTypePredicates<fvti>.Predicates in {
7424-
def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
7425-
(fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
7426-
(!cast<Instruction>("PseudoVFMV_S_"#fvti.ScalarSuffix#"_" #
7427-
fvti.LMul.MX)
7428-
(fvti.Vector $rs1),
7429-
(fvti.Scalar fvti.ScalarRegClass:$rs2),
7430-
GPR:$vl, fvti.Log2SEW)>;
7431-
7432-
def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
7433-
(fvti.Scalar (fpimm0)), VLOpFrag)),
7434-
(!cast<Instruction>("PseudoVMV_S_X_" # fvti.LMul.MX)
7435-
(fvti.Vector $rs1), (XLenVT X0), GPR:$vl, fvti.Log2SEW)>;
7436-
7437-
def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
7438-
(fvti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)),
7439-
(!cast<Instruction>("PseudoVMV_S_X_" # fvti.LMul.MX)
7440-
(fvti.Vector $rs1), GPR:$imm, GPR:$vl, fvti.Log2SEW)>;
7441-
}
7442-
}
7443-
74447418
//===----------------------------------------------------------------------===//
74457419
// 16.3. Vector Slide Instructions
74467420
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll

+18-18
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, ha
4848
define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
4949
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16:
5050
; CHECK: # %bb.0: # %entry
51-
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
51+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
5252
; CHECK-NEXT: vfmv.s.f v8, fa0
5353
; CHECK-NEXT: ret
5454
entry:
@@ -61,7 +61,7 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>,
6161
define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
6262
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16:
6363
; CHECK: # %bb.0: # %entry
64-
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
64+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
6565
; CHECK-NEXT: vfmv.s.f v8, fa0
6666
; CHECK-NEXT: ret
6767
entry:
@@ -74,7 +74,7 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>,
7474
define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {
7575
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16:
7676
; CHECK: # %bb.0: # %entry
77-
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
77+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
7878
; CHECK-NEXT: vfmv.s.f v8, fa0
7979
; CHECK-NEXT: ret
8080
entry:
@@ -113,7 +113,7 @@ declare <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float>,
113113
define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_nxv4f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
114114
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32:
115115
; CHECK: # %bb.0: # %entry
116-
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
116+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
117117
; CHECK-NEXT: vfmv.s.f v8, fa0
118118
; CHECK-NEXT: ret
119119
entry:
@@ -126,7 +126,7 @@ declare <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float>,
126126
define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_nxv8f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
127127
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32:
128128
; CHECK: # %bb.0: # %entry
129-
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
129+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
130130
; CHECK-NEXT: vfmv.s.f v8, fa0
131131
; CHECK-NEXT: ret
132132
entry:
@@ -139,7 +139,7 @@ declare <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float
139139
define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_nxv16f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {
140140
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32:
141141
; CHECK: # %bb.0: # %entry
142-
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
142+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
143143
; CHECK-NEXT: vfmv.s.f v8, fa0
144144
; CHECK-NEXT: ret
145145
entry:
@@ -165,7 +165,7 @@ declare <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double>
165165
define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_nxv2f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
166166
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64:
167167
; CHECK: # %bb.0: # %entry
168-
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
168+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
169169
; CHECK-NEXT: vfmv.s.f v8, fa0
170170
; CHECK-NEXT: ret
171171
entry:
@@ -178,7 +178,7 @@ declare <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double>
178178
define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_nxv4f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
179179
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64:
180180
; CHECK: # %bb.0: # %entry
181-
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
181+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
182182
; CHECK-NEXT: vfmv.s.f v8, fa0
183183
; CHECK-NEXT: ret
184184
entry:
@@ -191,7 +191,7 @@ declare <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double>
191191
define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_nxv8f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {
192192
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64:
193193
; CHECK: # %bb.0: # %entry
194-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
194+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
195195
; CHECK-NEXT: vfmv.s.f v8, fa0
196196
; CHECK-NEXT: ret
197197
entry:
@@ -235,7 +235,7 @@ entry:
235235
define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_zero_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
236236
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f16:
237237
; CHECK: # %bb.0: # %entry
238-
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
238+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
239239
; CHECK-NEXT: vmv.s.x v8, zero
240240
; CHECK-NEXT: ret
241241
entry:
@@ -246,7 +246,7 @@ entry:
246246
define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_zero_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
247247
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv16f16:
248248
; CHECK: # %bb.0: # %entry
249-
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
249+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
250250
; CHECK-NEXT: vmv.s.x v8, zero
251251
; CHECK-NEXT: ret
252252
entry:
@@ -257,7 +257,7 @@ entry:
257257
define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_zero_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
258258
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv32f16:
259259
; CHECK: # %bb.0: # %entry
260-
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
260+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
261261
; CHECK-NEXT: vmv.s.x v8, zero
262262
; CHECK-NEXT: ret
263263
entry:
@@ -290,7 +290,7 @@ entry:
290290
define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_zero_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
291291
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f32:
292292
; CHECK: # %bb.0: # %entry
293-
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
293+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
294294
; CHECK-NEXT: vmv.s.x v8, zero
295295
; CHECK-NEXT: ret
296296
entry:
@@ -301,7 +301,7 @@ entry:
301301
define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_zero_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
302302
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f32:
303303
; CHECK: # %bb.0: # %entry
304-
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
304+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
305305
; CHECK-NEXT: vmv.s.x v8, zero
306306
; CHECK-NEXT: ret
307307
entry:
@@ -312,7 +312,7 @@ entry:
312312
define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_zero_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
313313
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv16f32:
314314
; CHECK: # %bb.0: # %entry
315-
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
315+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
316316
; CHECK-NEXT: vmv.s.x v8, zero
317317
; CHECK-NEXT: ret
318318
entry:
@@ -334,7 +334,7 @@ entry:
334334
define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_zero_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
335335
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f64:
336336
; CHECK: # %bb.0: # %entry
337-
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
337+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
338338
; CHECK-NEXT: vmv.s.x v8, zero
339339
; CHECK-NEXT: ret
340340
entry:
@@ -345,7 +345,7 @@ entry:
345345
define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_zero_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
346346
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f64:
347347
; CHECK: # %bb.0: # %entry
348-
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
348+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
349349
; CHECK-NEXT: vmv.s.x v8, zero
350350
; CHECK-NEXT: ret
351351
entry:
@@ -356,7 +356,7 @@ entry:
356356
define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_zero_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
357357
; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f64:
358358
; CHECK: # %bb.0: # %entry
359-
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
359+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
360360
; CHECK-NEXT: vmv.s.x v8, zero
361361
; CHECK-NEXT: ret
362362
entry:

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -630,8 +630,9 @@ define void @add_v16i64(ptr %x, ptr %y) vscale_range(2,2) {
630630
define <vscale x 2 x float> @fp_reduction_vfmv_s_f(float %0, <vscale x 8 x float> %1, i64 %2) {
631631
; CHECK-LABEL: fp_reduction_vfmv_s_f:
632632
; CHECK: # %bb.0:
633-
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
633+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
634634
; CHECK-NEXT: vfmv.s.f v12, fa0
635+
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
635636
; CHECK-NEXT: vfredusum.vs v8, v8, v12
636637
; CHECK-NEXT: ret
637638
%4 = tail call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32.i64(<vscale x 8 x float> poison, float %0, i64 %2)

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