cpu/e132xs: More recompiler optimisation:

* Disabled single-instruction-per-block mode.
* Don't bother with delay slot checks where it's unnecessary.
* Try to generate a speicalised copy of the delay slot instruction
  followed by a direct branch of possible.
* Use the pre-decoded instruction length for updating the PC.
* Specialised versions of the CHK instruction that always or never
  raise exceptions.

Author: cuavas

src/devices/cpu/e132xs/e132xs.cpp

@@ -31,6 +31,7 @@
  - GMS30C2232
 
  TODO:
+ - Fix behaviour of branches in delay slots
  - Many wrong cycle counts
  - No emulation of memory access latency and pipleline
  - Should a zero bit shift clear C or leave it unchanged?

src/devices/cpu/e132xs/e132xs.h

@@ -38,7 +38,7 @@
 
 #define E132XS_STRICT_VERIFY            0x0001          /* verify all instructions */
 
-#define SINGLE_INSTRUCTION_MODE         (1)
+#define SINGLE_INSTRUCTION_MODE         (0)
 
 #define ENABLE_E132XS_DRC               (1)
 
@@ -486,12 +486,9 @@ class hyperstone_device : public cpu_device, public hyperstone_disassembler::con
 	bool generate_opcode(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
 
 	void generate_get_trap_addr(drcuml_block &block, uml::code_label &label, uml::parameter trapno);
-	void generate_check_delay_pc(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
 	uint32_t generate_get_const(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
 	uint32_t generate_get_immediate_s(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
-	void generate_ignore_immediate_s(drcuml_block &block, const opcode_desc *desc);
 	uint32_t generate_get_pcrel(drcuml_block &block, const opcode_desc *desc);
-	void generate_ignore_pcrel(drcuml_block &block, const opcode_desc *desc);
 
 	void generate_get_global_register(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
 	void generate_set_global_register(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint32_t dst_code);
@@ -507,8 +504,6 @@ class hyperstone_device : public cpu_device, public hyperstone_disassembler::con
 	void generate_update_flags_cmp(drcuml_block &block, compiler_state &compiler, uml::parameter sr);
 
 	template <trap_exception_or_int TYPE> void generate_trap_exception_or_int(drcuml_block &block, uml::code_label &label, uml::parameter trapno);
-	void generate_int(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint32_t addr);
-	void generate_exception(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint32_t addr);
 	void generate_software(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc);
 
 	void generate_trap_on_overflow(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uml::parameter sr);

src/devices/cpu/e132xs/e132xsdrc.cpp

@@ -15,6 +15,7 @@ struct hyperstone_device::compiler_state
 
 	const uint8_t   m_mode;
 	uml::code_label m_labelnum  = 1;
+	uint8_t         m_check_delay = 1;
 };
 
 
@@ -260,6 +261,7 @@ void hyperstone_device::code_compile_block(uint8_t mode, offs_t pc)
 				UML_MOV(block, I7, 0);
 
 				/* iterate over instructions in the sequence and compile them */
+				compiler.m_check_delay = 1;
 				for (const opcode_desc *curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next())
 				{
 					generate_sequence_instruction(block, compiler, curdesc);
@@ -759,10 +761,46 @@ void hyperstone_device::generate_sequence_instruction(drcuml_block &block, compi
 
 	if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
 	{
+		if (compiler.m_check_delay == 1)
+		{
+			// if PC is used in a delay instruction, the delayed PC should be used
+			const int nodelay = compiler.m_labelnum++;
+			const int done = compiler.m_labelnum++;
+			UML_TEST(block, mem(&m_core->delay_slot), 1);
+			UML_JMPc(block, uml::COND_Z, nodelay);
+			UML_MOV(block, DRC_PC, mem(&m_core->delay_pc));
+			UML_MOV(block, mem(&m_core->delay_slot), 0);
+			UML_MOV(block, mem(&m_core->delay_slot_taken), 1);
+			UML_JMP(block, done);
+			UML_LABEL(block, nodelay);
+			UML_ADD(block, DRC_PC, DRC_PC, desc->length);
+			UML_MOV(block, mem(&m_core->delay_slot_taken), 0);
+			UML_LABEL(block, done);
+		}
+		else
+		{
+			UML_ADD(block, DRC_PC, DRC_PC, desc->length);
+			UML_MOV(block, mem(&m_core->delay_slot_taken), 0);
+		}
+
 		// compile the instruction
-		if (!generate_opcode(block, compiler, desc))
+		if (generate_opcode(block, compiler, desc))
+		{
+			if (compiler.m_check_delay)
+			{
+				if (compiler.m_check_delay == 1)
+				{
+					UML_TEST(block, mem(&m_core->delay_slot_taken), ~uint32_t(0));
+					UML_CALLHc(block, uml::COND_NZ, *m_delay_taken[compiler.m_mode]);
+				}
+				--compiler.m_check_delay;
+			}
+
+			if (BIT(compiler.m_mode, 1) && !desc->delayslots)
+				UML_EXHc(block, uml::COND_Z, *m_exception, EXCEPTION_TRACE);
+		}
+		else
 		{
-			UML_MOV(block, DRC_PC, desc->pc);
 			UML_MOV(block, mem(&m_core->arg0), desc->opptr.w[0]);
 			UML_CALLC(block, &c_funcs::unimplemented, this);
 		}
@@ -775,8 +813,6 @@ bool hyperstone_device::generate_opcode(drcuml_block &block, compiler_state &com
 {
 	uint32_t op = (uint32_t)desc->opptr.w[0];
 
-	UML_ADD(block, DRC_PC, DRC_PC, 2);
-
 	switch (op >> 8)
 	{
 		case 0x00: generate_chk<GLOBAL, GLOBAL>(block, compiler, desc); break;
@@ -1039,14 +1075,5 @@ bool hyperstone_device::generate_opcode(drcuml_block &block, compiler_state &com
 
 	UML_ROLINS(block, DRC_SR, ((desc->length >> 1) << ILC_SHIFT) | P_MASK, 0, ILC_MASK | P_MASK);
 
-	UML_TEST(block, mem(&m_core->delay_slot_taken), ~uint32_t(0));
-	UML_CALLHc(block, uml::COND_NZ, *m_delay_taken[compiler.m_mode]);
-
-	if (BIT(compiler.m_mode, 1))
-	{
-		UML_TEST(block, mem(&m_core->delay_slot), 1);
-		UML_EXHc(block, uml::COND_Z, *m_exception, EXCEPTION_TRACE);
-	}
-
 	return true;
 }