[LTD toup] clock_control: stm32: fix a PLL init corner case

Commit 58c8d15 ("clock control:stm32: provide STM32Cube LL based
driver") added PLL initialization which disables the PLL before
configuring it.

This works if the system clock source is not the PLL (which is the
usual case for Zephyr booting out of chip reset). However, if the
SYSCLK source *is* the PLL, this halts execution.

To support this use case, switch the SYSCLK source to the
always-present HSI before disabling the PLL.

Signed-off-by: Marti Bolivar <[email protected]>

Author: Marti Bolivar

drivers/clock_control/stm32_ll_clock.c

@@ -190,7 +190,14 @@ static int stm32_clock_control_init(struct device *dev)
 	/* configure PLL input settings */
 	config_pll_init(&s_PLLInitStruct);
 
-	/* Disable PLL before configuration */
+	/*
+	 * Switch to HSI and disable the PLL before configuration.
+	 *
+	 * Don't use s_ClkInitStruct.AHBCLKDivider as the AHB
+	 * prescaler here. In this configuration, that's the value to
+	 * use when the SYSCLK source is the PLL, not HSI.
+	 */
+	stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1);
 	LL_RCC_PLL_Disable();
 
 #ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR