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Rename edge to slot (#171)
Parent PR: mmtk/mmtk-core#1134 --------- Co-authored-by: mmtkgc-bot <[email protected]>
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8 files changed

+94
-94
lines changed

8 files changed

+94
-94
lines changed

jikesrvm/rvm/src/org/jikesrvm/mm/mminterface/RustScanThread.java

+3-3
Original file line numberDiff line numberDiff line change
@@ -123,8 +123,8 @@
123123
private Address edges;
124124
private Word size = Word.zero();
125125
// The buffer size agreed between the Rust part and the Java part of the binding.
126-
// See the constant EDGES_BUFFER_CAPACITY in scanning.rs.
127-
public static final Word EDGES_BUFFER_CAPACITY = Word.fromIntZeroExtend(4096);
126+
// See the constant SLOTS_BUFFER_CAPACITY in scanning.rs.
127+
public static final Word SLOTS_BUFFER_CAPACITY = Word.fromIntZeroExtend(4096);
128128

129129
/***********************************************************************
130130
*
@@ -222,7 +222,7 @@ private void reportEdge(Address edge) {
222222
if (VM.VerifyAssertions) VM._assert(!this.edges.isZero());
223223
this.edges.plus(cursor.toInt() << LOG_BYTES_IN_WORD).store(edge);
224224
// Flush if full
225-
if (cursor.GE(EDGES_BUFFER_CAPACITY)) {
225+
if (cursor.GE(SLOTS_BUFFER_CAPACITY)) {
226226
flush();
227227
}
228228
}

mmtk/Cargo.lock

+23-23
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mmtk/Cargo.toml

+2-2
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ lto = true
1616
[package.metadata.jikesrvm]
1717
# Our CI matches the following line and extract mmtk/jikesrvm. If this line is updated, please check ci yaml files and make sure it works.
1818
jikesrvm_repo = "https://github.com/mmtk/jikesrvm.git"
19-
jikesrvm_version = "1191b3846b6528011bce12996bbb5e15a23a043f"
19+
jikesrvm_version = "f2d3178c2c74e8c8daeb105d98e48feac51dd44d"
2020

2121
[dependencies]
2222
libc = "0.2"
@@ -28,7 +28,7 @@ log = {version = "0.4", features = ["max_level_trace", "release_max_level_off"]
2828
# - change branch/rev
2929
# - change repo name
3030
# But other changes including adding/removing whitespaces in commented lines may break the CI.
31-
mmtk = { git = "https://github.com/mmtk/mmtk-core.git", rev = "dccce9063b57dde96d2e97670297aed4dc32e6e1" }
31+
mmtk = { git = "https://github.com/mmtk/mmtk-core.git", rev = "56b2521d2b99848ee0613a0a5288fe6d81b754ba" }
3232
# Uncomment the following to build locally - if you change the path locally, do not commit the change in a PR
3333
# mmtk = { path = "../repos/mmtk-core" }
3434

mmtk/src/api.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
use crate::scanning::EDGES_BUFFER_CAPACITY;
1+
use crate::scanning::SLOTS_BUFFER_CAPACITY;
22
use collection::VMCollection;
33
use collection::BOOT_THREAD;
44
use libc::c_char;
@@ -25,7 +25,7 @@ use SINGLETON;
2525
/// Caller needs to make sure the ptr is a valid vector pointer.
2626
#[no_mangle]
2727
pub unsafe extern "C" fn release_buffer(ptr: *mut Address) {
28-
let _vec = Vec::<Address>::from_raw_parts(ptr, 0, EDGES_BUFFER_CAPACITY);
28+
let _vec = Vec::<Address>::from_raw_parts(ptr, 0, SLOTS_BUFFER_CAPACITY);
2929
}
3030

3131
#[no_mangle]

mmtk/src/lib.rs

+5-5
Original file line numberDiff line numberDiff line change
@@ -43,11 +43,11 @@ pub static mut JTOC_BASE: Address = Address::ZERO;
4343
#[derive(Default)]
4444
pub struct JikesRVM;
4545

46-
/// The type of edges in JikesRVM.
46+
/// The type of slots in JikesRVM.
4747
///
4848
/// TODO: We start with Address to ease the transition.
49-
/// We should switch to the equivalent `mmtk::vm::edge_shape::SimpleEdge` later.
50-
pub type JikesRVMEdge = Address;
49+
/// We should switch to the equivalent `mmtk::vm::slot::SimpleSlot` later.
50+
pub type JikesRVMSlot = Address;
5151

5252
impl VMBinding for JikesRVM {
5353
type VMObjectModel = object_model::VMObjectModel;
@@ -56,8 +56,8 @@ impl VMBinding for JikesRVM {
5656
type VMActivePlan = active_plan::VMActivePlan;
5757
type VMReferenceGlue = reference_glue::VMReferenceGlue;
5858

59-
type VMEdge = JikesRVMEdge;
60-
type VMMemorySlice = mmtk::vm::edge_shape::UnimplementedMemorySlice<JikesRVMEdge>;
59+
type VMSlot = JikesRVMSlot;
60+
type VMMemorySlice = mmtk::vm::slot::UnimplementedMemorySlice<JikesRVMSlot>;
6161

6262
#[cfg(target_arch = "x86")]
6363
// On Intel we align code to 16 bytes as recommended in the optimization manual.

mmtk/src/scan_boot_image.rs

+18-18
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
use crate::scanning::EDGES_BUFFER_CAPACITY;
1+
use crate::scanning::SLOTS_BUFFER_CAPACITY;
22
use crate::unboxed_size_constants::*;
33
use crate::JikesRVM;
4-
use crate::JikesRVMEdge;
4+
use crate::JikesRVMSlot;
55
use entrypoint::*;
66
use java_size_constants::*;
77
use mmtk::scheduler::*;
@@ -26,7 +26,7 @@ static REFS: AtomicUsize = AtomicUsize::new(0);
2626

2727
pub fn scan_boot_image(
2828
_tls: OpaquePointer,
29-
factory: &mut impl RootsWorkFactory<JikesRVMEdge>,
29+
factory: &mut impl RootsWorkFactory<JikesRVMSlot>,
3030
subwork_id: usize,
3131
total_subwork: usize,
3232
) {
@@ -48,22 +48,22 @@ pub fn scan_boot_image(
4848
ROOTS.store(0, Ordering::Relaxed);
4949
REFS.store(0, Ordering::Relaxed);
5050

51-
let mut edges = vec![];
51+
let mut slots = vec![];
5252
while cursor < map_end {
5353
trace!("Processing chunk at {:x}", cursor);
54-
process_chunk(cursor, image_start, map_start, map_end, |edge| {
55-
edges.push(edge);
56-
if edges.len() >= EDGES_BUFFER_CAPACITY {
57-
let new_edges =
58-
mem::replace(&mut edges, Vec::with_capacity(EDGES_BUFFER_CAPACITY));
59-
factory.create_process_edge_roots_work(new_edges);
54+
process_chunk(cursor, image_start, map_start, map_end, |slot| {
55+
slots.push(slot);
56+
if slots.len() >= SLOTS_BUFFER_CAPACITY {
57+
let new_slots =
58+
mem::replace(&mut slots, Vec::with_capacity(SLOTS_BUFFER_CAPACITY));
59+
factory.create_process_roots_work(new_slots);
6060
}
6161
});
6262
trace!("Chunk processed successfully");
6363
cursor += stride;
6464
}
65-
if !edges.is_empty() {
66-
factory.create_process_edge_roots_work(edges);
65+
if !slots.is_empty() {
66+
factory.create_process_roots_work(slots);
6767
}
6868
}
6969
}
@@ -73,7 +73,7 @@ fn process_chunk(
7373
image_start: Address,
7474
_map_start: Address,
7575
map_end: Address,
76-
mut report_edge: impl FnMut(Address),
76+
mut report_slot: impl FnMut(Address),
7777
) {
7878
let mut value: usize;
7979
let mut offset: usize = 0;
@@ -106,7 +106,7 @@ fn process_chunk(
106106
if cfg!(feature = "debug") {
107107
ROOTS.fetch_add(1, Ordering::Relaxed);
108108
}
109-
report_edge(slot);
109+
report_slot(slot);
110110
}
111111
if runlength != 0 {
112112
for _ in 0..runlength {
@@ -121,7 +121,7 @@ fn process_chunk(
121121
ROOTS.fetch_add(1, Ordering::Relaxed);
122122
}
123123
// TODO: check_reference(slot) ?
124-
report_edge(slot);
124+
report_slot(slot);
125125
}
126126
}
127127
}
@@ -141,13 +141,13 @@ fn decode_long_encoding(cursor: Address) -> usize {
141141
}
142142
}
143143

144-
pub struct ScanBootImageRoots<F: RootsWorkFactory<JikesRVMEdge>> {
144+
pub struct ScanBootImageRoots<F: RootsWorkFactory<JikesRVMSlot>> {
145145
factory: F,
146146
subwork_id: usize,
147147
total_subwork: usize,
148148
}
149149

150-
impl<F: RootsWorkFactory<JikesRVMEdge>> ScanBootImageRoots<F> {
150+
impl<F: RootsWorkFactory<JikesRVMSlot>> ScanBootImageRoots<F> {
151151
pub fn new(factory: F, subwork_id: usize, total_subwork: usize) -> Self {
152152
Self {
153153
factory,
@@ -157,7 +157,7 @@ impl<F: RootsWorkFactory<JikesRVMEdge>> ScanBootImageRoots<F> {
157157
}
158158
}
159159

160-
impl<F: RootsWorkFactory<JikesRVMEdge>> GCWork<JikesRVM> for ScanBootImageRoots<F> {
160+
impl<F: RootsWorkFactory<JikesRVMSlot>> GCWork<JikesRVM> for ScanBootImageRoots<F> {
161161
fn do_work(&mut self, _worker: &mut GCWorker<JikesRVM>, _mmtk: &'static MMTK<JikesRVM>) {
162162
scan_boot_image(
163163
OpaquePointer::UNINITIALIZED,

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