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[interpreter] Implement extadd pairwise instructions
These 4 instructions: - i32x4.extadd_pairwise_i16x8_s - i32x4.extadd_pairwise_i16x8_u - i16x8.extadd_pairwise_i8x16_s - i16x8.extadd_pairwise_i8x16_u were merged in WebAssembly#380. Drive-by cleanup to meta/README.md to list all generated files.
1 parent b2e0c76 commit ae8d840

15 files changed

+282
-17
lines changed

‎interpreter/binary/decode.ml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -399,6 +399,8 @@ let simd_prefix s =
399399
| 0xa2l -> i64x2_abs
400400
| 0xa3l -> i32x4_all_true
401401
| 0xa4l -> i32x4_bitmask
402+
| 0xa5l -> i32x4_extadd_pairwise_i16x8_s
403+
| 0xa6l -> i32x4_extadd_pairwise_i16x8_u
402404
| 0xa7l -> i32x4_widen_low_i16x8_s
403405
| 0xa8l -> i32x4_widen_high_i16x8_s
404406
| 0xa9l -> i32x4_widen_low_i16x8_u
@@ -420,6 +422,8 @@ let simd_prefix s =
420422
| 0xbfl -> i32x4_extmul_high_i16x8_u
421423
| 0xc0l -> i64x2_eq
422424
| 0xc1l -> i64x2_neg
425+
| 0xc2l -> i16x8_extadd_pairwise_i8x16_s
426+
| 0xc3l -> i16x8_extadd_pairwise_i8x16_u
423427
| 0xc4l -> i64x2_bitmask
424428
| 0xc7l -> i64x2_widen_low_i32x4_s
425429
| 0xc8l -> i64x2_widen_high_i32x4_s

‎interpreter/binary/encode.ml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -354,12 +354,16 @@ let encode m =
354354
| Unary (V128 V128Op.(I16x8 WidenHighS)) -> simd_op 0x88l
355355
| Unary (V128 V128Op.(I16x8 WidenLowU)) -> simd_op 0x89l
356356
| Unary (V128 V128Op.(I16x8 WidenHighU)) -> simd_op 0x8al
357+
| Unary (V128 V128Op.(I16x8 ExtAddPairwiseS)) -> simd_op 0xc2l
358+
| Unary (V128 V128Op.(I16x8 ExtAddPairwiseU)) -> simd_op 0xc3l
357359
| Unary (V128 V128Op.(I32x4 Abs)) -> simd_op 0xa0l
358360
| Unary (V128 V128Op.(I32x4 Neg)) -> simd_op 0xa1l
359361
| Unary (V128 V128Op.(I32x4 WidenLowS)) -> simd_op 0xa7l
360362
| Unary (V128 V128Op.(I32x4 WidenHighS)) -> simd_op 0xa8l
361363
| Unary (V128 V128Op.(I32x4 WidenLowU)) -> simd_op 0xa9l
362364
| Unary (V128 V128Op.(I32x4 WidenHighU)) -> simd_op 0xaal
365+
| Unary (V128 V128Op.(I32x4 ExtAddPairwiseS)) -> simd_op 0xa5l
366+
| Unary (V128 V128Op.(I32x4 ExtAddPairwiseU)) -> simd_op 0xa6l
363367
| Unary (V128 V128Op.(I64x2 Abs)) -> simd_op 0xa2l
364368
| Unary (V128 V128Op.(I64x2 Neg)) -> simd_op 0xc1l
365369
| Unary (V128 V128Op.(I64x2 WidenLowS)) -> simd_op 0xc7l

‎interpreter/exec/eval_simd.ml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,8 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
2323
| I16x8 WidenHighS -> to_value (SXX.I16x8_convert.widen_high_s (of_value 1 v))
2424
| I16x8 WidenLowU -> to_value (SXX.I16x8_convert.widen_low_u (of_value 1 v))
2525
| I16x8 WidenHighU -> to_value (SXX.I16x8_convert.widen_high_u (of_value 1 v))
26+
| I16x8 ExtAddPairwiseS -> to_value (SXX.I16x8_convert.extadd_pairwise_s (of_value 1 v))
27+
| I16x8 ExtAddPairwiseU -> to_value (SXX.I16x8_convert.extadd_pairwise_u (of_value 1 v))
2628
| I32x4 Abs -> to_value (SXX.I32x4.abs (of_value 1 v))
2729
| I32x4 Neg -> to_value (SXX.I32x4.neg (of_value 1 v))
2830
| I32x4 WidenLowS -> to_value (SXX.I32x4_convert.widen_low_s (of_value 1 v))
@@ -35,6 +37,8 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
3537
to_value (SXX.I32x4_convert.trunc_sat_f64x2_s_zero (of_value 1 v))
3638
| I32x4 TruncSatF64x2UZero ->
3739
to_value (SXX.I32x4_convert.trunc_sat_f64x2_u_zero (of_value 1 v))
40+
| I32x4 ExtAddPairwiseS -> to_value (SXX.I32x4_convert.extadd_pairwise_s (of_value 1 v))
41+
| I32x4 ExtAddPairwiseU -> to_value (SXX.I32x4_convert.extadd_pairwise_u (of_value 1 v))
3842
| I64x2 Abs -> to_value (SXX.I64x2.abs (of_value 1 v))
3943
| I64x2 Neg -> to_value (SXX.I64x2.neg (of_value 1 v))
4044
| I64x2 WidenLowS -> to_value (SXX.I64x2_convert.widen_low_s (of_value 1 v))

‎interpreter/exec/simd.ml

Lines changed: 29 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,8 @@ sig
183183
val extmul_high_s : t -> t -> t
184184
val extmul_low_u : t -> t -> t
185185
val extmul_high_u : t -> t -> t
186+
val extadd_pairwise_s : t -> t
187+
val extadd_pairwise_u : t -> t
186188
end
187189
module I32x4_convert : sig
188190
val trunc_sat_f32x4_s : t -> t
@@ -198,6 +200,8 @@ sig
198200
val extmul_high_s : t -> t -> t
199201
val extmul_low_u : t -> t -> t
200202
val extmul_high_u : t -> t -> t
203+
val extadd_pairwise_s : t -> t
204+
val extadd_pairwise_u : t -> t
201205
end
202206
module I64x2_convert : sig
203207
val widen_low_s : t -> t
@@ -436,17 +440,23 @@ struct
436440
let narrow_s = narrow Rep.to_i32x4 Rep.of_i16x8 I16.saturate_s
437441
let narrow_u = narrow Rep.to_i32x4 Rep.of_i16x8 I16.saturate_u
438442

439-
let widen take_or_drop mask x =
440-
Rep.of_i16x8 (List.map (Int32.logand mask) (take_or_drop 8 (Rep.to_i8x16 x)))
441-
let widen_low_s = widen Lib.List.take 0xffffffffl
442-
let widen_high_s = widen Lib.List.drop 0xffffffffl
443-
let widen_low_u = widen Lib.List.take 0xffl
444-
let widen_high_u = widen Lib.List.drop 0xffl
443+
let ext_s = Int32.logand 0xffffffffl
444+
let ext_u = Int32.logand 0xffl
445+
446+
let widen take_or_drop ext x = Rep.of_i16x8 (List.map ext (take_or_drop 8 (Rep.to_i8x16 x)))
447+
let widen_low_s = widen Lib.List.take ext_s
448+
let widen_high_s = widen Lib.List.drop ext_s
449+
let widen_low_u = widen Lib.List.take ext_u
450+
let widen_high_u = widen Lib.List.drop ext_u
445451

446452
let extmul_low_s x y = I16x8.mul (widen_low_s x) (widen_low_s y)
447453
let extmul_high_s x y = I16x8.mul (widen_high_s x) (widen_high_s y)
448454
let extmul_low_u x y = I16x8.mul (widen_low_u x) (widen_low_u y)
449455
let extmul_high_u x y = I16x8.mul (widen_high_u x) (widen_high_u y)
456+
457+
let extadd ext x y = Int32.add (ext x) (ext y)
458+
let extadd_pairwise_s x = Rep.of_i16x8 (Lib.List.pairwise (extadd ext_s) (Rep.to_i8x16 x))
459+
let extadd_pairwise_u x = Rep.of_i16x8 (Lib.List.pairwise (extadd ext_u) (Rep.to_i8x16 x))
450460
end
451461

452462
module I32x4_convert = struct
@@ -459,12 +469,15 @@ struct
459469
let trunc_sat_f64x2_s_zero = convert_zero I32_convert.trunc_sat_f64_s
460470
let trunc_sat_f64x2_u_zero = convert_zero I32_convert.trunc_sat_f64_u
461471

462-
let widen take_or_drop mask x =
463-
Rep.of_i32x4 (List.map (Int32.logand mask) (take_or_drop 4 (Rep.to_i16x8 x)))
464-
let widen_low_s = widen Lib.List.take 0xffffffffl
465-
let widen_high_s = widen Lib.List.drop 0xffffffffl
466-
let widen_low_u = widen Lib.List.take 0xffffl
467-
let widen_high_u = widen Lib.List.drop 0xffffl
472+
let ext_s = Int32.logand 0xffffffffl
473+
let ext_u = Int32.logand 0xffffl
474+
475+
let widen take_or_drop ext x =
476+
Rep.of_i32x4 (List.map ext (take_or_drop 4 (Rep.to_i16x8 x)))
477+
let widen_low_s = widen Lib.List.take ext_s
478+
let widen_high_s = widen Lib.List.drop ext_s
479+
let widen_low_u = widen Lib.List.take ext_u
480+
let widen_high_u = widen Lib.List.drop ext_u
468481

469482
let dot_i16x8_s x y =
470483
let xs = Rep.to_i16x8 x in
@@ -481,6 +494,10 @@ struct
481494
let extmul_high_s x y = I32x4.mul (widen_high_s x) (widen_high_s y)
482495
let extmul_low_u x y = I32x4.mul (widen_low_u x) (widen_low_u y)
483496
let extmul_high_u x y = I32x4.mul (widen_high_u x) (widen_high_u y)
497+
498+
let extadd ext x y = Int32.add (ext x) (ext y)
499+
let extadd_pairwise_s x = Rep.of_i32x4 (Lib.List.pairwise (extadd ext_s) (Rep.to_i16x8 x))
500+
let extadd_pairwise_u x = Rep.of_i32x4 (Lib.List.pairwise (extadd ext_u) (Rep.to_i16x8 x))
484501
end
485502

486503
module I64x2_convert = struct

‎interpreter/syntax/ast.ml

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@@ -51,6 +51,7 @@ struct
5151
type iunop = Abs | Neg | TruncSatF32x4S | TruncSatF32x4U
5252
| WidenLowS | WidenLowU | WidenHighS | WidenHighU
5353
| Popcnt | TruncSatF64x2SZero | TruncSatF64x2UZero
54+
| ExtAddPairwiseS | ExtAddPairwiseU
5455
type ibinop = Add | Sub | MinS | MinU | MaxS | MaxU | Mul | AvgrU
5556
| Eq | Ne | LtS | LtU | LeS | LeU | GtS | GtU | GeS | GeU
5657
| Swizzle | Shuffle of int list | NarrowS | NarrowU

‎interpreter/syntax/operators.ml

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Original file line numberDiff line numberDiff line change
@@ -355,6 +355,8 @@ let i16x8_extmul_high_i8x16_s = Binary (V128 V128Op.(I16x8 ExtMulHighS))
355355
let i16x8_extmul_low_i8x16_u = Binary (V128 V128Op.(I16x8 ExtMulLowU))
356356
let i16x8_extmul_high_i8x16_u = Binary (V128 V128Op.(I16x8 ExtMulHighU))
357357
let i16x8_q15mulr_sat_s = Binary (V128 V128Op.(I16x8 Q15MulRSatS))
358+
let i16x8_extadd_pairwise_i8x16_s = Unary (V128 V128Op.(I16x8 ExtAddPairwiseS))
359+
let i16x8_extadd_pairwise_i8x16_u = Unary (V128 V128Op.(I16x8 ExtAddPairwiseU))
358360

359361
let i32x4_splat = Convert (V128 V128Op.(I32x4 Splat))
360362
let i32x4_extract_lane imm = SimdExtract (V128Op.I32x4 (ZX, imm))
@@ -396,6 +398,8 @@ let i32x4_extmul_low_i16x8_s = Binary (V128 V128Op.(I32x4 ExtMulLowS))
396398
let i32x4_extmul_high_i16x8_s = Binary (V128 V128Op.(I32x4 ExtMulHighS))
397399
let i32x4_extmul_low_i16x8_u = Binary (V128 V128Op.(I32x4 ExtMulLowU))
398400
let i32x4_extmul_high_i16x8_u = Binary (V128 V128Op.(I32x4 ExtMulHighU))
401+
let i32x4_extadd_pairwise_i16x8_s = Unary (V128 V128Op.(I32x4 ExtAddPairwiseS))
402+
let i32x4_extadd_pairwise_i16x8_u = Unary (V128 V128Op.(I32x4 ExtAddPairwiseU))
399403

400404
let i64x2_splat = Convert (V128 V128Op.(I64x2 Splat))
401405
let i64x2_extract_lane imm = SimdExtract (V128Op.I64x2 (ZX, imm))

‎interpreter/text/arrange.ml

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Original file line numberDiff line numberDiff line change
@@ -210,6 +210,8 @@ struct
210210
| I16x8 WidenHighS -> "i16x8.widen_high_i8x16_s"
211211
| I16x8 WidenLowU -> "i16x8.widen_low_i8x16_u"
212212
| I16x8 WidenHighU -> "i16x8.widen_high_i8x16_u"
213+
| I16x8 ExtAddPairwiseS -> "i16x8.extadd_pairwise_i8x16_s"
214+
| I16x8 ExtAddPairwiseU -> "i16x8.extadd_pairwise_i8x16_u"
213215
| I32x4 Abs -> "i32x4.abs"
214216
| I32x4 Neg -> "i32x4.neg"
215217
| I32x4 WidenLowS -> "i32x4.widen_low_i16x8_s"
@@ -220,6 +222,8 @@ struct
220222
| I32x4 TruncSatF32x4U -> "i32x4.trunc_sat_f32x4_u"
221223
| I32x4 TruncSatF64x2SZero -> "i32x4.trunc_sat_f64x2_s_zero"
222224
| I32x4 TruncSatF64x2UZero -> "i32x4.trunc_sat_f64x2_u_zero"
225+
| I32x4 ExtAddPairwiseS -> "i32x4.extadd_pairwise_i16x8_s"
226+
| I32x4 ExtAddPairwiseU -> "i32x4.extadd_pairwise_i16x8_u"
223227
| I64x2 Abs -> "i64x2.abs"
224228
| I64x2 Neg -> "i64x2.neg"
225229
| I64x2 WidenLowS -> "i64x2.widen_low_i32x4_s"

‎interpreter/text/lexer.mll

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@@ -604,6 +604,11 @@ rule token = parse
604604
| "i16x8.q15mulr_sat_s"
605605
{ BINARY i16x8_q15mulr_sat_s }
606606

607+
| "i16x8.extadd_pairwise_i8x16_"(sign as s)
608+
{ UNARY (ext s i16x8_extadd_pairwise_i8x16_s i16x8_extadd_pairwise_i8x16_u) }
609+
| "i32x4.extadd_pairwise_i16x8_"(sign as s)
610+
{ UNARY (ext s i32x4_extadd_pairwise_i16x8_s i32x4_extadd_pairwise_i16x8_u) }
611+
607612
| (simd_shape as s) { SIMD_SHAPE (simd_shape s) }
608613

609614
| name as s { VAR s }

‎interpreter/util/lib.ml

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Original file line numberDiff line numberDiff line change
@@ -105,6 +105,11 @@ struct
105105
let rec concat_map f = function
106106
| [] -> []
107107
| x::xs -> f x @ concat_map f xs
108+
109+
let rec pairwise f = function
110+
| [] -> []
111+
| x1::x2::xs -> f x1 x2 :: pairwise f xs
112+
| _ -> failwith "pairwise"
108113
end
109114

110115
module List32 =

‎interpreter/util/lib.mli

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Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ sig
2222
val index_where : ('a -> bool) -> 'a list -> int option
2323
val map_filter : ('a -> 'b option) -> 'a list -> 'b list
2424
val concat_map : ('a -> 'b list) -> 'a list -> 'b list
25+
val pairwise : ('a -> 'a -> 'b) -> 'a list -> 'b list
2526
end
2627

2728
module List32 :

‎test/core/simd/meta/README.md

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,28 @@ Currently it only support following simd test files generation.
2222
- 'simd_i16x8_sat_arith.wast'
2323
- 'simd_f32x4.wast'
2424
- 'simd_f64x2.wast'
25-
- 'simd_f32x4_rounding'
26-
- 'simd_f64x2_rounding'
27-
- 'simd_f32x4_pmin_pmax'
28-
- 'simd_f64x2_pmin_pmax'
29-
- 'simd_i32x4_dot_i16x8'
25+
- 'simd_f32x4_rounding.wast'
26+
- 'simd_f64x2_rounding.wast'
27+
- 'simd_f32x4_pmin_pmax.wast'
28+
- 'simd_f64x2_pmin_pmax.wast'
29+
- 'simd_i32x4_dot_i16x8.wast'
30+
- 'simd_load8_lane.wast'
31+
- 'simd_load16_lane.wast'
32+
- 'simd_load32_lane.wast'
33+
- 'simd_load64_lane.wast,
34+
- 'simd_store8_lane.wast'
35+
- 'simd_store16_lane.wast'
36+
- 'simd_store32_lane.wast'
37+
- 'simd_store64_lane.wast,
38+
- 'simd_i16x8_extmul_i8x16.wast'
39+
- 'simd_i32x4_extmul_i16x8.wast'
40+
- 'simd_i64x2_extmul_i32x4.wast'
41+
- 'simd_int_to_int_widen.wast'
42+
- 'simd_i32x4_trunc_sat_f32x4.wast'
43+
- 'simd_i32x4_trunc_sat_f64x2.wast'
44+
- 'simd_i16x8_q15mulr_sat_s.wast',
45+
- 'simd_i16x8_extadd_pairwise_i8x16.wast',
46+
- 'simd_i32x4_extadd_pairwise_i16x8.wast',
3047

3148

3249
Usage:

‎test/core/simd/meta/gen_tests.py

Lines changed: 1 addition & 0 deletions
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@@ -38,6 +38,7 @@
3838
'simd_int_to_int_widen',
3939
'simd_int_trunc_sat_float',
4040
'simd_i16x8_q15mulr_sat_s',
41+
'simd_extadd_pairwise',
4142
)
4243

4344

‎test/core/simd/meta/simd_extadd_pairwise.py

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
#!/usr/bin/env python3
2+
3+
from simd_arithmetic import SimdArithmeticCase, i16
4+
from simd_integer_op import ArithmeticOp
5+
6+
7+
class SimdExtAddPairwise(SimdArithmeticCase):
8+
BINARY_OPS = ()
9+
10+
def unary_op(self, x, signed):
11+
# For test data we always splat a single value to the
12+
# entire v128, so doubling the input works.
13+
return ArithmeticOp.get_valid_value(x, self.src_lane, signed=signed) * 2
14+
15+
@property
16+
def hex_unary_op_test_data(self):
17+
return []
18+
19+
@property
20+
def unary_test_data(self):
21+
return [
22+
(self.normal_unary_op_test_data, [self.SRC_LANE_TYPE,self.LANE_TYPE]),
23+
]
24+
25+
def get_case_data(self):
26+
case_data = []
27+
for op in self.UNARY_OPS:
28+
op_name = self.op_name(op)
29+
case_data.append(['#', op_name])
30+
for data_group, v128_forms in self.unary_test_data:
31+
for data in data_group:
32+
case_data.append([op_name, [str(data)],
33+
str(self.unary_op(data, op.endswith('s'))),
34+
v128_forms])
35+
return case_data
36+
37+
def get_combine_cases(self):
38+
return ''
39+
40+
def gen_test_cases(self):
41+
wast_filename = '../simd_{}_extadd_pairwise_{}.wast'.format(self.LANE_TYPE, self.SRC_LANE_TYPE)
42+
with open(wast_filename, 'w') as fp:
43+
fp.write(self.get_all_cases())
44+
45+
class SimdI16x8ExtAddPairwise(SimdExtAddPairwise):
46+
UNARY_OPS = ('extadd_pairwise_i8x16_s','extadd_pairwise_i8x16_u')
47+
LANE_TYPE = 'i16x8'
48+
SRC_LANE_TYPE = 'i8x16'
49+
50+
class SimdI32x4ExtAddPairwise(SimdExtAddPairwise):
51+
UNARY_OPS = ('extadd_pairwise_i16x8_s','extadd_pairwise_i16x8_u')
52+
LANE_TYPE = 'i32x4'
53+
SRC_LANE_TYPE = 'i16x8'
54+
55+
def gen_test_cases():
56+
simd_i16x8_arith = SimdI16x8ExtAddPairwise()
57+
simd_i32x4_arith = SimdI32x4ExtAddPairwise()
58+
simd_i16x8_arith.gen_test_cases()
59+
simd_i32x4_arith.gen_test_cases()
60+
61+
if __name__ == '__main__':
62+
gen_test_cases()

‎test/core/simd/simd_i16x8_extadd_pairwise_i8x16.wast

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
;; Tests for i16x8 arithmetic operations on major boundary values and all special values.
2+
3+
4+
(module
5+
(func (export "i16x8.extadd_pairwise_i8x16_s") (param v128) (result v128) (i16x8.extadd_pairwise_i8x16_s (local.get 0)))
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(func (export "i16x8.extadd_pairwise_i8x16_u") (param v128) (result v128) (i16x8.extadd_pairwise_i8x16_u (local.get 0)))
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)
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;; i16x8.extadd_pairwise_i8x16_s
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0))
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(v128.const i16x8 0 0 0 0 0 0 0 0))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1))
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(v128.const i16x8 2 2 2 2 2 2 2 2))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1))
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(v128.const i16x8 -2 -2 -2 -2 -2 -2 -2 -2))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 126 126 126 126 126 126 126 126 126 126 126 126 126 126 126 126))
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(v128.const i16x8 252 252 252 252 252 252 252 252))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127))
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(v128.const i16x8 -254 -254 -254 -254 -254 -254 -254 -254))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128))
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(v128.const i16x8 -256 -256 -256 -256 -256 -256 -256 -256))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127))
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(v128.const i16x8 254 254 254 254 254 254 254 254))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_s" (v128.const i8x16 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255))
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(v128.const i16x8 -2 -2 -2 -2 -2 -2 -2 -2))
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;; i16x8.extadd_pairwise_i8x16_u
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0))
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(v128.const i16x8 0 0 0 0 0 0 0 0))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1))
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(v128.const i16x8 2 2 2 2 2 2 2 2))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1))
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(v128.const i16x8 510 510 510 510 510 510 510 510))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 126 126 126 126 126 126 126 126 126 126 126 126 126 126 126 126))
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(v128.const i16x8 252 252 252 252 252 252 252 252))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127 -127))
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(v128.const i16x8 258 258 258 258 258 258 258 258))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128))
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(v128.const i16x8 256 256 256 256 256 256 256 256))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127))
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(v128.const i16x8 254 254 254 254 254 254 254 254))
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(assert_return (invoke "i16x8.extadd_pairwise_i8x16_u" (v128.const i8x16 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255))
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(v128.const i16x8 510 510 510 510 510 510 510 510))
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;; type check
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(assert_invalid (module (func (result v128) (i16x8.extadd_pairwise_i8x16_s (i32.const 0)))) "type mismatch")
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(assert_invalid (module (func (result v128) (i16x8.extadd_pairwise_i8x16_u (i32.const 0)))) "type mismatch")
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;; Test operation with empty argument
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(assert_invalid
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(module
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(func $i16x8.extadd_pairwise_i8x16_s-arg-empty (result v128)
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(i16x8.extadd_pairwise_i8x16_s)
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)
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)
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"type mismatch"
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)
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(assert_invalid
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(module
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(func $i16x8.extadd_pairwise_i8x16_u-arg-empty (result v128)
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(i16x8.extadd_pairwise_i8x16_u)
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)
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)
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"type mismatch"
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)
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