Skip to content

Commit befe99e

Browse files
committed
[interpreter] Implement i64x2.abs
This was merged in WebAssembly#413.
1 parent 17f55c3 commit befe99e

File tree

8 files changed

+17
-4
lines changed

8 files changed

+17
-4
lines changed

interpreter/binary/decode.ml

+1
Original file line numberDiff line numberDiff line change
@@ -375,6 +375,7 @@ let simd_prefix s =
375375
| 0x9fl -> i16x8_extmul_high_i8x16_u
376376
| 0xa0l -> i32x4_abs
377377
| 0xa1l -> i32x4_neg
378+
| 0xa2l -> i64x2_abs
378379
| 0xa3l -> i32x4_all_true
379380
| 0xa4l -> i32x4_bitmask
380381
| 0xa7l -> i32x4_widen_low_i16x8_s

interpreter/binary/encode.ml

+1
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,7 @@ let encode m =
350350
| Unary (V128 V128Op.(I32x4 WidenHighS)) -> simd_op 0xa8l
351351
| Unary (V128 V128Op.(I32x4 WidenLowU)) -> simd_op 0xa9l
352352
| Unary (V128 V128Op.(I32x4 WidenHighU)) -> simd_op 0xaal
353+
| Unary (V128 V128Op.(I64x2 Abs)) -> simd_op 0xa2l
353354
| Unary (V128 V128Op.(I64x2 Neg)) -> simd_op 0xc1l
354355
| Unary (V128 V128Op.(I64x2 WidenLowS)) -> simd_op 0xc7l
355356
| Unary (V128 V128Op.(I64x2 WidenHighS)) -> simd_op 0xc8l

interpreter/exec/eval_simd.ml

+1
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
3131
| I32x4 WidenHighU -> to_value (SXX.I32x4_convert.widen_high_u (of_value 1 v))
3232
| I32x4 TruncSatF32x4S -> to_value (SXX.I32x4_convert.trunc_sat_f32x4_s (of_value 1 v))
3333
| I32x4 TruncSatF32x4U -> to_value (SXX.I32x4_convert.trunc_sat_f32x4_u (of_value 1 v))
34+
| I64x2 Abs -> to_value (SXX.I64x2.abs (of_value 1 v))
3435
| I64x2 Neg -> to_value (SXX.I64x2.neg (of_value 1 v))
3536
| I64x2 WidenLowS -> to_value (SXX.I64x2_convert.widen_low_s (of_value 1 v))
3637
| I64x2 WidenHighS -> to_value (SXX.I64x2_convert.widen_high_s (of_value 1 v))

interpreter/syntax/operators.ml

+1
Original file line numberDiff line numberDiff line change
@@ -398,6 +398,7 @@ let i64x2_lt_s = Binary (V128 V128Op.(I64x2 LtS))
398398
let i64x2_le_s = Binary (V128 V128Op.(I64x2 LeS))
399399
let i64x2_gt_s = Binary (V128 V128Op.(I64x2 GtS))
400400
let i64x2_ge_s = Binary (V128 V128Op.(I64x2 GeS))
401+
let i64x2_abs = Unary (V128 V128Op.(I64x2 Abs))
401402
let i64x2_neg = Unary (V128 V128Op.(I64x2 Neg))
402403
let i64x2_bitmask = SimdBitmask Simd.I64x2
403404
let i64x2_add = Binary (V128 V128Op.(I64x2 Add))

interpreter/text/arrange.ml

+1
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,7 @@ struct
217217
| I32x4 WidenHighU -> "i32x4.widen_high_i16x8_u"
218218
| I32x4 TruncSatF32x4S -> "i32x4.trunc_sat_f32x4_s"
219219
| I32x4 TruncSatF32x4U -> "i32x4.trunc_sat_f32x4_u"
220+
| I64x2 Abs -> "i64x2.abs"
220221
| I64x2 Neg -> "i64x2.neg"
221222
| I64x2 WidenLowS -> "i64x2.widen_low_i32x4_s"
222223
| I64x2 WidenHighS -> "i64x2.widen_high_i32x4_s"

interpreter/text/lexer.mll

+1-2
Original file line numberDiff line numberDiff line change
@@ -526,8 +526,7 @@ rule token = parse
526526
| (simd_float_shape as s)".min" { BINARY (simd_float_op s f32x4_min f64x2_min) }
527527
| (simd_float_shape as s)".max" { BINARY (simd_float_op s f32x4_max f64x2_max) }
528528
| (simd_shape as s)".abs"
529-
{ only ["i8x16"; "i16x8"; "i32x4"; "f32x4"; "f64x2"] s lexbuf;
530-
UNARY (simdop s i8x16_abs i16x8_abs i32x4_abs unreachable f32x4_abs f64x2_abs) }
529+
{ UNARY (simdop s i8x16_abs i16x8_abs i32x4_abs i64x2_abs f32x4_abs f64x2_abs) }
531530
| "i8x16.popcnt"
532531
{ UNARY i8x16_popcnt }
533532
| (simd_int_shape as s)".all_true"

test/core/simd/meta/simd_int_arith2.py

+11-1
Original file line numberDiff line numberDiff line change
@@ -523,6 +523,14 @@ def gen_test_cases(self):
523523
fp.write(self.get_all_cases())
524524

525525

526+
class Simdi64x2Case(SimdLaneWiseInteger):
527+
LANE_TYPE = 'i64x2'
528+
class_summary = """;; Tests for {lane_type} [abs] operations."""
529+
BINARY_OPS = ()
530+
531+
UNKNOWN_BINARY_OPS = ()
532+
533+
526534
class Simdi32x4Case(SimdLaneWiseInteger):
527535
LANE_TYPE = 'i32x4'
528536
class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u, abs] operations."""
@@ -537,7 +545,6 @@ class Simdi16x8Case(SimdLaneWiseInteger):
537545

538546
BINARY_OPS = ('min_s', 'min_u', 'max_s', 'max_u', 'avgr_u')
539547
UNKNOWN_BINARY_OPS = ('i16x8.avgr', 'i16x8.avgr_s')
540-
UNKNOWN_UNARY_OPS = ('i64x2.abs',)
541548

542549

543550
class Simdi8x16Case(SimdLaneWiseInteger):
@@ -551,6 +558,9 @@ class Simdi8x16Case(SimdLaneWiseInteger):
551558

552559

553560
def gen_test_cases():
561+
simd_i64x2_case = Simdi64x2Case()
562+
simd_i64x2_case.gen_test_cases()
563+
554564
simd_i32x4_case = Simdi32x4Case()
555565
simd_i32x4_case.gen_test_cases()
556566

test/core/simd/simd_i16x8_arith2.wast

-1
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,6 @@
336336
;; Unknown operators
337337
(assert_malformed (module quote "(memory 1) (func (result v128) (i16x8.avgr (v128.const i16x8 0 0 0 0 0 0 0 0) (v128.const i16x8 1 1 1 1 1 1 1 1)))") "unknown operator")
338338
(assert_malformed (module quote "(memory 1) (func (result v128) (i16x8.avgr_s (v128.const i16x8 0 0 0 0 0 0 0 0) (v128.const i16x8 1 1 1 1 1 1 1 1)))") "unknown operator")
339-
(assert_malformed (module quote "(memory 1) (func (result v128) (i64x2.abs (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)))") "unknown operator")
340339

341340
;; Type check
342341
(assert_invalid (module (func (result v128) (i16x8.min_s (i32.const 0) (f32.const 0.0)))) "type mismatch")

0 commit comments

Comments
 (0)