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[spectext] Add {f32x4,f64x2}.{pmin,pmax}
We added these instructions to the syntax in WebAssembly#353, this adds them to the other sections, numerics, text, binary.
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‎document/core/appendix/gen-index-instructions.py

+4
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@@ -511,6 +511,8 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\F32X4.\VDIV', r'\hex{FD}~~231', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fdiv'),
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Instruction(r'\F32X4.\VMIN', r'\hex{FD}~~232', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmin'),
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Instruction(r'\F32X4.\VMAX', r'\hex{FD}~~233', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmax'),
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Instruction(r'\F32X4.\VPMIN', r'\hex{FD}~~234', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'),
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Instruction(r'\F32X4.\VPMAX', r'\hex{FD}~~235', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'),
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Instruction(r'\F64X2.\VABS', r'\hex{FD}~~236', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fabs'),
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Instruction(r'\F64X2.\VNEG', r'\hex{FD}~~237', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fneg'),
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Instruction(r'\F64X2.\VSQRT', r'\hex{FD}~~239', r'[\V128] \to [\I32]', r'valid-vunop', r'exec-vunop', r'op-fsqrt'),
@@ -519,6 +521,8 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\F64X2.\VMUL', r'\hex{FD}~~242', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmul'),
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Instruction(r'\F64X2.\VDIV', r'\hex{FD}~~243', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fdiv'),
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Instruction(r'\F64X2.\VMIN', r'\hex{FD}~~244', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmin'),
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Instruction(r'\F64X2.\VPMIN', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'),
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Instruction(r'\F64X2.\VPMAX', r'\hex{FD}~~246', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'),
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Instruction(r'\F64X2.\VMAX', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmax'),
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Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_s}', r'\hex{FD}~~248', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-trunc_sat_s'),
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Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_u}', r'\hex{FD}~~249', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-trunc_sat_u'),

‎document/core/appendix/index-instructions.rst

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@@ -459,6 +459,8 @@ Instruction Binary Opcode Type
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:math:`\F32X4.\VDIV` :math:`\hex{FD}~~231` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fdiv>`
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:math:`\F32X4.\VMIN` :math:`\hex{FD}~~232` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fmin>`
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:math:`\F32X4.\VMAX` :math:`\hex{FD}~~233` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fmax>`
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:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~234` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fpmin>`
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:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~235` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fpmax>`
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:math:`\F64X2.\VABS` :math:`\hex{FD}~~236` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-fabs>`
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:math:`\F64X2.\VNEG` :math:`\hex{FD}~~237` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-fneg>`
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:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~239` :math:`[\V128] \to [\I32]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-fsqrt>`
@@ -467,6 +469,8 @@ Instruction Binary Opcode Type
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:math:`\F64X2.\VMUL` :math:`\hex{FD}~~242` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fmul>`
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:math:`\F64X2.\VDIV` :math:`\hex{FD}~~243` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fdiv>`
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:math:`\F64X2.\VMIN` :math:`\hex{FD}~~244` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fmin>`
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:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~245` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fpmin>`
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:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~246` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fpmax>`
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:math:`\F64X2.\VMAX` :math:`\hex{FD}~~245` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-vbinop>`, :ref:`operator <op-fmax>`
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:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~248` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-trunc_sat_s>`
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:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~249` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-trunc_sat_u>`

‎document/core/binary/instructions.rst

+6-2
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@@ -721,7 +721,9 @@ All other SIMD instructions are plain opcodes without any immediates.
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\hex{FD}~~230{:}\Bu32 &\Rightarrow& \F32X4.\VMUL \\ &&|&
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\hex{FD}~~231{:}\Bu32 &\Rightarrow& \F32X4.\VDIV \\ &&|&
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\hex{FD}~~232{:}\Bu32 &\Rightarrow& \F32X4.\VMIN \\ &&|&
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\hex{FD}~~233{:}\Bu32 &\Rightarrow& \F32X4.\VMAX \\
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\hex{FD}~~233{:}\Bu32 &\Rightarrow& \F32X4.\VMAX \\ &&|&
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\hex{FD}~~234{:}\Bu32 &\Rightarrow& \F32X4.\VPMIN \\ &&|&
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\hex{FD}~~235{:}\Bu32 &\Rightarrow& \F32X4.\VPMAX \\
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\end{array}
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.. math::
@@ -735,7 +737,9 @@ All other SIMD instructions are plain opcodes without any immediates.
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\hex{FD}~~242{:}\Bu32 &\Rightarrow& \F64X2.\VMUL \\ &&|&
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\hex{FD}~~243{:}\Bu32 &\Rightarrow& \F64X2.\VDIV \\ &&|&
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\hex{FD}~~244{:}\Bu32 &\Rightarrow& \F64X2.\VMIN \\ &&|&
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\hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VMAX \\
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\hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VMAX \\ &&|&
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\hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VPMIN \\ &&|&
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\hex{FD}~~246{:}\Bu32 &\Rightarrow& \F64X2.\VPMAX \\
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\end{array}
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.. math::

‎document/core/exec/numerics.rst

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@@ -1675,6 +1675,38 @@ This non-deterministic result is expressed by the following auxiliary function p
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\end{array}
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.. _op-fpmin:
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:math:`\fpmin_N(z_1, z_2)`
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..........................
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* If :math:`z_2` is less than :math:`z_1` then return :math:`z_2`.
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* Else return :math:`z_1`.
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.. math::
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\begin{array}{@{}lcll}
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\fpmin_N(z_1, z_2) &=& z_2 & (\iff \flt_N(z_2, z_1) = 1) \\
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\fpmin_N(z_1, z_2) &=& z_1 & (\otherwise)
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\end{array}
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.. _op-fpmax:
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:math:`\fpmax_N(z_1, z_2)`
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..........................
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* If :math:`z_1` is less than :math:`z_2` then return :math:`z_2`.
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* Else return :math:`z_1`.
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.. math::
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\begin{array}{@{}lcll}
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\fpmax_N(z_1, z_2) &=& z_2 & (\iff \flt_N(z_1, z_2) = 1) \\
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\fpmax_N(z_1, z_2) &=& z_1 & (\otherwise)
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\end{array}
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.. _convert-ops:
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Conversions

‎document/core/text/instructions.rst

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@@ -755,7 +755,9 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
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\text{f32x4.mul} &\Rightarrow& \F32X4.\VMUL\\ &&|&
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\text{f32x4.div} &\Rightarrow& \F32X4.\VDIV\\ &&|&
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\text{f32x4.min} &\Rightarrow& \F32X4.\VMIN\\ &&|&
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\text{f32x4.max} &\Rightarrow& \F32X4.\VMAX\\
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\text{f32x4.max} &\Rightarrow& \F32X4.\VMAX\\ &&|&
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\text{f32x4.pmin} &\Rightarrow& \F32X4.\VPMIN\\ &&|&
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\text{f32x4.pmax} &\Rightarrow& \F32X4.\VPMAX\\
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\end{array}
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.. math::
@@ -769,7 +771,9 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
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\text{f64x2.mul} &\Rightarrow& \F64X2.\VMUL\\ &&|&
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\text{f64x2.div} &\Rightarrow& \F64X2.\VDIV\\ &&|&
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\text{f64x2.min} &\Rightarrow& \F64X2.\VMIN\\ &&|&
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\text{f64x2.max} &\Rightarrow& \F64X2.\VMAX\\
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\text{f64x2.max} &\Rightarrow& \F64X2.\VMAX\\ &&|&
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\text{f64x2.pmin} &\Rightarrow& \F64X2.\VPMIN\\ &&|&
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\text{f64x2.pmax} &\Rightarrow& \F64X2.\VPMAX\\
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\end{array}
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.. math::

‎document/core/util/macros.def

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@@ -420,6 +420,8 @@
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.. |VDIV| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{div}}
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.. |VMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{min}}
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.. |VMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{max}}
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.. |VPMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{pmin}}
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.. |VPMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{pmax}}
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.. |NARROW| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{narrow}}
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.. |WIDEN| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{widen}}
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.. |AVGR| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{avgr}}
@@ -1056,6 +1058,8 @@
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.. |fgt| mathdef:: \xref{exec/numerics}{op-fgt}{\F{fgt}}
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.. |fle| mathdef:: \xref{exec/numerics}{op-fle}{\F{fle}}
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.. |fge| mathdef:: \xref{exec/numerics}{op-fge}{\F{fge}}
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.. |fpmin| mathdef:: \xref{exec/numerics}{op-fpmin}{\F{fpmin}}
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.. |fpmax| mathdef:: \xref{exec/numerics}{op-fpmax}{\F{fpmax}}
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.. |extend| mathdef:: \xref{exec/numerics}{op-extend_u}{\F{extend}}
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.. |extendu| mathdef:: \xref{exec/numerics}{op-extend_u}{\F{extend}^{\K{u}}}

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