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[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.
Summary: This change enables all kind of carry out ISD opcodes to be selected according to the node divergence. Reviewers: rampitec, arsenm, vpykhtin Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78091
1 parent 283658c commit 5b898bd

15 files changed

+964
-297
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

+38-11
Original file line numberDiff line numberDiff line change
@@ -1039,24 +1039,51 @@ void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) {
10391039
SDValue RHS = N->getOperand(1);
10401040
SDValue CI = N->getOperand(2);
10411041

1042-
unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64
1043-
: AMDGPU::V_SUBB_U32_e64;
1044-
CurDAG->SelectNodeTo(
1045-
N, Opc, N->getVTList(),
1046-
{LHS, RHS, CI, CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
1042+
if (N->isDivergent()) {
1043+
unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64
1044+
: AMDGPU::V_SUBB_U32_e64;
1045+
CurDAG->SelectNodeTo(
1046+
N, Opc, N->getVTList(),
1047+
{LHS, RHS, CI,
1048+
CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
1049+
} else {
1050+
unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::S_ADD_CO_PSEUDO
1051+
: AMDGPU::S_SUB_CO_PSEUDO;
1052+
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), {LHS, RHS, CI});
1053+
}
10471054
}
10481055

10491056
void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
10501057
// The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
10511058
// carry out despite the _i32 name. These were renamed in VI to _U32.
10521059
// FIXME: We should probably rename the opcodes here.
1053-
unsigned Opc = N->getOpcode() == ISD::UADDO ?
1054-
AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
1060+
bool IsAdd = N->getOpcode() == ISD::UADDO;
1061+
bool IsVALU = N->isDivergent();
1062+
1063+
for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;
1064+
++UI)
1065+
if (UI.getUse().getResNo() == 1) {
1066+
if ((IsAdd && (UI->getOpcode() != ISD::ADDCARRY)) ||
1067+
(!IsAdd && (UI->getOpcode() != ISD::SUBCARRY))) {
1068+
IsVALU = true;
1069+
break;
1070+
}
1071+
}
10551072

1056-
CurDAG->SelectNodeTo(
1057-
N, Opc, N->getVTList(),
1058-
{N->getOperand(0), N->getOperand(1),
1059-
CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
1073+
if (IsVALU) {
1074+
unsigned Opc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
1075+
1076+
CurDAG->SelectNodeTo(
1077+
N, Opc, N->getVTList(),
1078+
{N->getOperand(0), N->getOperand(1),
1079+
CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
1080+
} else {
1081+
unsigned Opc = N->getOpcode() == ISD::UADDO ? AMDGPU::S_UADDO_PSEUDO
1082+
: AMDGPU::S_USUBO_PSEUDO;
1083+
1084+
CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
1085+
{N->getOperand(0), N->getOperand(1)});
1086+
}
10601087
}
10611088

10621089
void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

+6
Original file line numberDiff line numberDiff line change
@@ -916,6 +916,12 @@ bool GCNPassConfig::addInstSelector() {
916916
AMDGPUPassConfig::addInstSelector();
917917
addPass(&SIFixSGPRCopiesID);
918918
addPass(createSILowerI1CopiesPass());
919+
// TODO: We have to add FinalizeISel
920+
// to expand V_ADD/SUB_U64_PSEUDO before SIFixupVectorISel
921+
// that expects V_ADD/SUB -> A_ADDC/SUBB pairs expanded.
922+
// Will be removed as soon as SIFixupVectorISel is changed
923+
// to work with V_ADD/SUB_U64_PSEUDO instead.
924+
addPass(&FinalizeISelID);
919925
addPass(createSIFixupVectorISelPass());
920926
addPass(createSIAddIMGInitPass());
921927
return false;

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

+153-22
Original file line numberDiff line numberDiff line change
@@ -3602,6 +3602,26 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
36023602
}
36033603

36043604
switch (MI.getOpcode()) {
3605+
case AMDGPU::S_UADDO_PSEUDO:
3606+
case AMDGPU::S_USUBO_PSEUDO: {
3607+
const DebugLoc &DL = MI.getDebugLoc();
3608+
MachineOperand &Dest0 = MI.getOperand(0);
3609+
MachineOperand &Dest1 = MI.getOperand(1);
3610+
MachineOperand &Src0 = MI.getOperand(2);
3611+
MachineOperand &Src1 = MI.getOperand(3);
3612+
3613+
unsigned Opc = (MI.getOpcode() == AMDGPU::S_UADDO_PSEUDO)
3614+
? AMDGPU::S_ADD_I32
3615+
: AMDGPU::S_SUB_I32;
3616+
BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
3617+
3618+
BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B64), Dest1.getReg())
3619+
.addImm(1)
3620+
.addImm(0);
3621+
3622+
MI.eraseFromParent();
3623+
return BB;
3624+
}
36053625
case AMDGPU::S_ADD_U64_PSEUDO:
36063626
case AMDGPU::S_SUB_U64_PSEUDO: {
36073627
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
@@ -3617,35 +3637,146 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
36173637
Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
36183638
Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
36193639

3620-
MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3621-
Src0, BoolRC, AMDGPU::sub0,
3622-
&AMDGPU::SReg_32RegClass);
3623-
MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3624-
Src0, BoolRC, AMDGPU::sub1,
3625-
&AMDGPU::SReg_32RegClass);
3640+
MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
3641+
MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3642+
MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
3643+
MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
36263644

3627-
MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3628-
Src1, BoolRC, AMDGPU::sub0,
3629-
&AMDGPU::SReg_32RegClass);
3630-
MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3631-
Src1, BoolRC, AMDGPU::sub1,
3632-
&AMDGPU::SReg_32RegClass);
3645+
MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
3646+
MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3647+
MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
3648+
MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
36333649

36343650
bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
36353651

36363652
unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
36373653
unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3638-
BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3639-
.add(Src0Sub0)
3640-
.add(Src1Sub0);
3641-
BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3642-
.add(Src0Sub1)
3643-
.add(Src1Sub1);
3654+
BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
3655+
BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1);
36443656
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3645-
.addReg(DestSub0)
3646-
.addImm(AMDGPU::sub0)
3647-
.addReg(DestSub1)
3648-
.addImm(AMDGPU::sub1);
3657+
.addReg(DestSub0)
3658+
.addImm(AMDGPU::sub0)
3659+
.addReg(DestSub1)
3660+
.addImm(AMDGPU::sub1);
3661+
MI.eraseFromParent();
3662+
return BB;
3663+
}
3664+
case AMDGPU::V_ADD_U64_PSEUDO:
3665+
case AMDGPU::V_SUB_U64_PSEUDO: {
3666+
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3667+
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3668+
const SIRegisterInfo *TRI = ST.getRegisterInfo();
3669+
const DebugLoc &DL = MI.getDebugLoc();
3670+
3671+
bool IsAdd = (MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO);
3672+
3673+
const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3674+
3675+
Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3676+
Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3677+
3678+
Register CarryReg = MRI.createVirtualRegister(CarryRC);
3679+
Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
3680+
3681+
MachineOperand &Dest = MI.getOperand(0);
3682+
MachineOperand &Src0 = MI.getOperand(1);
3683+
MachineOperand &Src1 = MI.getOperand(2);
3684+
3685+
const TargetRegisterClass *Src0RC = Src0.isReg()
3686+
? MRI.getRegClass(Src0.getReg())
3687+
: &AMDGPU::VReg_64RegClass;
3688+
const TargetRegisterClass *Src1RC = Src1.isReg()
3689+
? MRI.getRegClass(Src1.getReg())
3690+
: &AMDGPU::VReg_64RegClass;
3691+
3692+
const TargetRegisterClass *Src0SubRC =
3693+
TRI->getSubRegClass(Src0RC, AMDGPU::sub0);
3694+
const TargetRegisterClass *Src1SubRC =
3695+
TRI->getSubRegClass(Src1RC, AMDGPU::sub1);
3696+
3697+
MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
3698+
MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
3699+
MachineOperand SrcReg1Sub0 = TII->buildExtractSubRegOrImm(
3700+
MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
3701+
3702+
MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
3703+
MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
3704+
MachineOperand SrcReg1Sub1 = TII->buildExtractSubRegOrImm(
3705+
MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
3706+
3707+
unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
3708+
MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3709+
.addReg(CarryReg, RegState::Define)
3710+
.add(SrcReg0Sub0)
3711+
.add(SrcReg1Sub0)
3712+
.addImm(0); // clamp bit
3713+
3714+
unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
3715+
MachineInstr *HiHalf =
3716+
BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3717+
.addReg(DeadCarryReg, RegState::Define | RegState::Dead)
3718+
.add(SrcReg0Sub1)
3719+
.add(SrcReg1Sub1)
3720+
.addReg(CarryReg, RegState::Kill)
3721+
.addImm(0); // clamp bit
3722+
3723+
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3724+
.addReg(DestSub0)
3725+
.addImm(AMDGPU::sub0)
3726+
.addReg(DestSub1)
3727+
.addImm(AMDGPU::sub1);
3728+
TII->legalizeOperands(*LoHalf);
3729+
TII->legalizeOperands(*HiHalf);
3730+
MI.eraseFromParent();
3731+
return BB;
3732+
}
3733+
case AMDGPU::S_ADD_CO_PSEUDO:
3734+
case AMDGPU::S_SUB_CO_PSEUDO: {
3735+
// This pseudo has a chance to be selected
3736+
// only from uniform add/subcarry node. All the VGPR operands
3737+
// therefore assumed to be splat vectors.
3738+
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3739+
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3740+
const SIRegisterInfo *TRI = ST.getRegisterInfo();
3741+
MachineBasicBlock::iterator MII = MI;
3742+
const DebugLoc &DL = MI.getDebugLoc();
3743+
MachineOperand &Dest = MI.getOperand(0);
3744+
MachineOperand &Src0 = MI.getOperand(2);
3745+
MachineOperand &Src1 = MI.getOperand(3);
3746+
MachineOperand &Src2 = MI.getOperand(4);
3747+
unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
3748+
? AMDGPU::S_ADDC_U32
3749+
: AMDGPU::S_SUBB_U32;
3750+
if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
3751+
Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3752+
BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0)
3753+
.addReg(Src0.getReg());
3754+
Src0.setReg(RegOp0);
3755+
}
3756+
if (Src1.isReg() && TRI->isVectorRegister(MRI, Src1.getReg())) {
3757+
Register RegOp1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3758+
BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp1)
3759+
.addReg(Src1.getReg());
3760+
Src1.setReg(RegOp1);
3761+
}
3762+
Register RegOp2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3763+
if (TRI->isVectorRegister(MRI, Src2.getReg())) {
3764+
BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp2)
3765+
.addReg(Src2.getReg());
3766+
Src2.setReg(RegOp2);
3767+
}
3768+
3769+
if (TRI->getRegSizeInBits(*MRI.getRegClass(Src2.getReg())) == 64) {
3770+
BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U64))
3771+
.addReg(Src2.getReg())
3772+
.addImm(0);
3773+
} else {
3774+
BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMPK_LG_U32))
3775+
.addReg(Src2.getReg())
3776+
.addImm(0);
3777+
}
3778+
3779+
BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1);
36493780
MI.eraseFromParent();
36503781
return BB;
36513782
}

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+80-3
Original file line numberDiff line numberDiff line change
@@ -5166,6 +5166,64 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst,
51665166
splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);
51675167
Inst.eraseFromParent();
51685168
continue;
5169+
5170+
// TODO: remove as soon as everything is ready
5171+
// to replace VGPR to SGPR copy with V_READFIRSTLANEs.
5172+
// S_ADD/SUB_CO_PSEUDO as well as S_UADDO/USUBO_PSEUDO
5173+
// can only be selected from the uniform SDNode.
5174+
case AMDGPU::S_ADD_CO_PSEUDO:
5175+
case AMDGPU::S_SUB_CO_PSEUDO: {
5176+
unsigned Opc = (Inst.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
5177+
? AMDGPU::V_ADDC_U32_e64
5178+
: AMDGPU::V_SUBB_U32_e64;
5179+
const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5180+
Register DummyCReg = MRI.createVirtualRegister(CarryRC);
5181+
Register CarryReg = MRI.createVirtualRegister(CarryRC);
5182+
Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass(
5183+
MRI.getRegClass(Inst.getOperand(0).getReg())));
5184+
BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY), CarryReg)
5185+
.addReg(Inst.getOperand(4).getReg());
5186+
MachineInstr *CarryOp =
5187+
BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(Opc), DestReg)
5188+
.addReg(DummyCReg, RegState::Define | RegState::Dead)
5189+
.add(Inst.getOperand(2))
5190+
.add(Inst.getOperand(3))
5191+
.addReg(CarryReg, RegState::Kill)
5192+
.addImm(0);
5193+
legalizeOperands(*CarryOp);
5194+
MRI.replaceRegWith(Inst.getOperand(0).getReg(), DestReg);
5195+
addUsersToMoveToVALUWorklist(DestReg, MRI, Worklist);
5196+
Inst.eraseFromParent();
5197+
}
5198+
continue;
5199+
case AMDGPU::S_UADDO_PSEUDO:
5200+
case AMDGPU::S_USUBO_PSEUDO: {
5201+
const DebugLoc &DL = Inst.getDebugLoc();
5202+
MachineOperand &Dest0 = Inst.getOperand(0);
5203+
MachineOperand &Dest1 = Inst.getOperand(1);
5204+
MachineOperand &Src0 = Inst.getOperand(2);
5205+
MachineOperand &Src1 = Inst.getOperand(3);
5206+
5207+
unsigned Opc = (Inst.getOpcode() == AMDGPU::S_UADDO_PSEUDO)
5208+
? AMDGPU::V_ADD_I32_e64
5209+
: AMDGPU::V_SUB_I32_e64;
5210+
const TargetRegisterClass *NewRC =
5211+
RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg()));
5212+
Register DestReg = MRI.createVirtualRegister(NewRC);
5213+
MachineInstr *NewInstr = BuildMI(*MBB, &Inst, DL, get(Opc), DestReg)
5214+
.addReg(Dest1.getReg(), RegState::Define)
5215+
.add(Src0)
5216+
.add(Src1)
5217+
.addImm(0); // clamp bit
5218+
5219+
legalizeOperands(*NewInstr, MDT);
5220+
5221+
MRI.replaceRegWith(Dest0.getReg(), DestReg);
5222+
addUsersToMoveToVALUWorklist(NewInstr->getOperand(0).getReg(), MRI,
5223+
Worklist);
5224+
Inst.eraseFromParent();
5225+
}
5226+
continue;
51695227
}
51705228

51715229
if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
@@ -5890,18 +5948,37 @@ void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
58905948
// Ensure that def inst defines SCC, which is still live.
58915949
assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
58925950
!Op.isDead() && Op.getParent() == &SCCDefInst);
5951+
SmallVector<MachineInstr *, 4> CopyToDelete;
58935952
// This assumes that all the users of SCC are in the same block
58945953
// as the SCC def.
58955954
for (MachineInstr &MI : // Skip the def inst itself.
58965955
make_range(std::next(MachineBasicBlock::iterator(SCCDefInst)),
58975956
SCCDefInst.getParent()->end())) {
58985957
// Check if SCC is used first.
5899-
if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1)
5900-
Worklist.insert(&MI);
5958+
if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1) {
5959+
if (MI.isCopy()) {
5960+
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
5961+
unsigned DestReg = MI.getOperand(0).getReg();
5962+
SmallVector<MachineInstr *, 4> Users;
5963+
for (auto &User : MRI.use_nodbg_instructions(DestReg)) {
5964+
if ((User.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO) ||
5965+
(User.getOpcode() == AMDGPU::S_SUB_CO_PSEUDO)) {
5966+
Users.push_back(&User);
5967+
Worklist.insert(&User);
5968+
}
5969+
}
5970+
for (auto &U : Users)
5971+
U->getOperand(4).setReg(RI.getVCC());
5972+
CopyToDelete.push_back(&MI);
5973+
} else
5974+
Worklist.insert(&MI);
5975+
}
59015976
// Exit if we find another SCC def.
59025977
if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
5903-
return;
5978+
break;
59045979
}
5980+
for (auto &Copy : CopyToDelete)
5981+
Copy->eraseFromParent();
59055982
}
59065983

59075984
const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(

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