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6 | 6 | //
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7 | 7 | //===----------------------------------------------------------------------===//
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8 | 8 |
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9 |
| -// REQUIRES: opencl-aot, ocloc, aoc, cpu, gpu, accelerator, llvm-link, llvm-spirv |
| 9 | +// REQUIRES: opencl-aot, ocloc, aoc, cpu, gpu, accelerator |
10 | 10 | // UNSUPPORTED: cuda
|
11 | 11 | // CUDA is not compatible with SPIR.
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12 | 12 |
|
13 |
| -// 1-command compilation case |
14 |
| -// Targeting CPU, GPU, FPGA |
15 |
| -// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %S/Inputs/aot.cpp -o %t_all.out |
16 |
| -// RUN: %HOST_RUN_PLACEHOLDER %t_all.out |
17 |
| -// RUN: %CPU_RUN_PLACEHOLDER %t_all.out |
18 |
| -// RUN: %GPU_RUN_PLACEHOLDER %t_all.out |
19 |
| -// RUN: %ACC_RUN_PLACEHOLDER %t_all.out |
| 13 | +// Produce a fat object for all targets (generic SPIR-V, CPU, GPU, FPGA) |
| 14 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_x86_64,spir64_gen,spir64_fpga %S/Inputs/aot.cpp -c -o %t.o |
20 | 15 |
|
21 |
| -// FIXME: Change the behavior when proper automation for assert support is |
22 |
| -// introduced. For the time being, AOT flow can't detect if specific extension |
23 |
| -// is available for this or that device. The automation to be introduced is to |
24 |
| -// query native binary generator on specific features. |
25 |
| -// |
26 |
| -// Produce object file, spirv, device images to combine these differently |
27 |
| -// at link-time, thus testing various AOT-compiled images configurations |
28 |
| -// Disable DAE when performing separate compilation here, as we are not |
29 |
| -// using sycl-post-link to fully enable. |
30 |
| -// RUN: %clangxx -fsycl -fno-sycl-dead-args-optimization %S/Inputs/aot.cpp -c -o %t.o |
31 |
| -// RUN: %clangxx -fsycl -fsycl-link-targets=spir64 %t.o -o %t.spv |
32 |
| -// AOT-compile device binary images |
33 |
| -// Neither of AOT tools can compile several files, hence, here is this |
34 |
| -// workaround |
35 |
| -// RUN: %llvm_spirv -r %sycl_libs_dir/libsycl-fallback-cassert.spv -o=%T/fallback-cassert.bc |
36 |
| -// RUN: %llvm_spirv -r %t.spv -o=%t.bc |
37 |
| -// RUN: %llvm_link %t.bc %T/fallback-cassert.bc -o=%t2.bc |
38 |
| -// RUN: %llvm_spirv %t2.bc -o=%t.spv |
39 |
| -// RUN: opencl-aot %t.spv -o=%t_cpu.ir --device=cpu |
40 |
| -// RUN: ocloc -file %t.spv -spirv_input -output %t_gen.out -output_no_suffix -device cfl |
41 |
| -// RUN: aoc %t.spv -o %t_fpga.aocx -sycl -dep-files=%t.d |
| 16 | +// CPU, GPU, FPGA |
| 17 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_all_aot.out |
| 18 | +// RUN: %HOST_RUN_PLACEHOLDER %t_all_aot.out |
| 19 | +// RUN: %CPU_RUN_PLACEHOLDER %t_all_aot.out |
| 20 | +// RUN: %GPU_RUN_PLACEHOLDER %t_all_aot.out |
| 21 | +// RUN: %ACC_RUN_PLACEHOLDER %t_all_aot.out |
42 | 22 |
|
43 | 23 | // CPU, GPU
|
44 |
| -// RUN: %clangxx -fsycl -fsycl-add-targets=spir64_x86_64:%t_cpu.ir,spir64_gen:%t_gen.out %t.o -o %t_cpu_gpu.out |
| 24 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_gen -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_cpu_gpu.out |
45 | 25 | // RUN: %HOST_RUN_PLACEHOLDER %t_cpu_gpu.out
|
46 | 26 | // RUN: %CPU_RUN_PLACEHOLDER %t_cpu_gpu.out
|
47 | 27 | // RUN: %GPU_RUN_PLACEHOLDER %t_cpu_gpu.out
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48 | 28 |
|
49 | 29 | // CPU, FPGA
|
50 |
| -// RUN: %clangxx -fsycl -fsycl-add-targets=spir64_x86_64:%t_cpu.ir,spir64_fpga:%t_fpga.aocx %t.o -o %t_cpu_fpga.out |
| 30 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_fpga %t.o -o %t_cpu_fpga.out |
51 | 31 | // RUN: %HOST_RUN_PLACEHOLDER %t_cpu_fpga.out
|
52 | 32 | // RUN: %CPU_RUN_PLACEHOLDER %t_cpu_fpga.out
|
53 | 33 | // RUN: %ACC_RUN_PLACEHOLDER %t_cpu_fpga.out
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54 | 34 |
|
55 | 35 | // GPU, FPGA
|
56 |
| -// RUN: %clangxx -fsycl -fsycl-add-targets=spir64_gen:%t_gen.out,spir64_fpga:%t_fpga.aocx %t.o -o %t_gpu_fpga.out |
| 36 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_gpu_fpga.out |
57 | 37 | // RUN: %HOST_RUN_PLACEHOLDER %t_gpu_fpga.out
|
58 | 38 | // RUN: %GPU_RUN_PLACEHOLDER %t_gpu_fpga.out
|
59 | 39 | // RUN: %ACC_RUN_PLACEHOLDER %t_gpu_fpga.out
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60 | 40 |
|
61 | 41 | // No AOT-compiled image for CPU
|
62 |
| -// RUN: %clangxx -fsycl -fsycl-add-targets=spir64:%t.spv,spir64_gen:%t_gen.out,spir64_fpga:%t_fpga.aocx %t.o -o %t_spv_gpu_fpga.out |
| 42 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_spv_gpu_fpga.out |
63 | 43 | // RUN: %CPU_RUN_PLACEHOLDER %t_spv_gpu_fpga.out
|
64 | 44 | // Check that execution on AOT-compatible devices is unaffected
|
65 | 45 | // RUN: %GPU_RUN_PLACEHOLDER %t_spv_gpu_fpga.out
|
66 | 46 | // RUN: %ACC_RUN_PLACEHOLDER %t_spv_gpu_fpga.out
|
67 | 47 |
|
68 | 48 | // No AOT-compiled image for GPU
|
69 |
| -// RUN: %clangxx -fsycl -fsycl-add-targets=spir64:%t.spv,spir64_x86_64:%t_cpu.ir,spir64_fpga:%t_fpga.aocx %t.o -o %t_spv_cpu_fpga.out |
| 49 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_x86_64,spir64_fpga %t.o -o %t_spv_cpu_fpga.out |
70 | 50 | // RUN: %GPU_RUN_PLACEHOLDER %t_spv_cpu_fpga.out
|
71 | 51 | // Check that execution on AOT-compatible devices is unaffected
|
72 | 52 | // RUN: %CPU_RUN_PLACEHOLDER %t_spv_cpu_fpga.out
|
73 | 53 | // RUN: %ACC_RUN_PLACEHOLDER %t_spv_cpu_fpga.out
|
74 | 54 |
|
75 | 55 | // No AOT-compiled image for FPGA
|
76 |
| -// RUN: %clangxx -fsycl -fsycl-add-targets=spir64:%t.spv,spir64_x86_64:%t_cpu.ir,spir64_gen:%t_gen.out %t.o -o %t_spv_cpu_gpu.out |
| 56 | +// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_x86_64,spir64_gen -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_spv_cpu_gpu.out |
77 | 57 | // RUN: %ACC_RUN_PLACEHOLDER %t_spv_cpu_gpu.out
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78 | 58 | // Check that execution on AOT-compatible devices is unaffected
|
79 | 59 | // RUN: %CPU_RUN_PLACEHOLDER %t_spv_cpu_gpu.out
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