Merge pull request #2607 from MikeOpenHWGroup/cv32e40p/dev_restore_verilator

Restore verilator to CV32E40P core testbench

Author: MikeOpenHWGroup

cv32e40p/sim/core/Makefile

@@ -134,15 +134,15 @@ SIMV                    = ./simv
 # dsim is the Metrics Technologies SystemVerilog simulator  (https://metrics.ca/)
 DSIM                    = dsim
 DSIM_HOME               = /tools/Metrics/dsim
-DSIM_CMP_FLAGS          = +define+CORE_TB -timescale 1ns/1ps $(SV_CMP_FLAGS) -suppress MultiBlockWrite +define+CV32E40P_APU_TRACE
+DSIM_CMP_FLAGS          = +define+CORE_TB +define+CV32E40P_APU_TRACE +acc+b -timescale 1ns/1ps $(SV_CMP_FLAGS)
+DSIM_SUPPRESS           = -suppress MultiBlockWrite -suppress IneffectiveDynamicCast
 DSIM_RUN_FLAGS          =
 DSIM_UVM_ARGS           = +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv
 DSIM_RESULTS           ?= $(PWD)/dsim_results
 DSIM_WORK              ?= $(DSIM_RESULTS)/dsim_work
 DSIM_IMAGE              = dsim.out
 
 ifneq (${WAVES}, 0)
-  DSIM_CMP_FLAGS += +acc
   DSIM_DMP_FILE  ?= dsim.fst
   DSIM_RUN_FLAGS += -waves $(DSIM_DMP_FILE)
 endif
@@ -155,7 +155,8 @@ XRUN_DIR          = xcelium.d
 # verilator configuration
 VERILATOR           = verilator
 VERI_FLAGS         +=
-VERI_COMPILE_FLAGS += -Wno-BLKANDNBLK $(SV_CMP_FLAGS) # hope this doesn't hurt us in the long run
+VERI_COMPILE_FLAGS += $(SV_CMP_FLAGS)
+VERI_WARN_WAIVERS  ?= --Wno-lint --Wno-UNOPTFLAT --Wno-MODDUP --Wno-MULTIDRIVEN --Wno-COMBDLY --Wno-BLKANDNBLK
 VERI_TRACE         ?=
 VERI_OBJ_DIR       ?= cobj_dir
 #VERI_LOG_DIR       ?= cobj_dir/logs
@@ -185,7 +186,7 @@ TBSRC_TOP   := $(TBSRC_HOME)/core/tb_top.sv
 TBSRC_CORE  := $(TBSRC_HOME)/core
 TBSRC_PKG   := $(TBSRC_CORE)/tb_riscv/include/perturbation_defines.sv
 TBSRC       := $(TBSRC_CORE)/tb_top.sv \
-               $(TBSRC_CORE)/cv32e40p_tb_wrapper.sv \
+               $(TBSRC_CORE)/cv32e40p_core_tb_wrapper.sv \
                $(TBSRC_CORE)/mm_ram.sv \
                $(TBSRC_CORE)/dp_ram.sv \
                $(TBSRC_CORE)/tb_riscv/riscv_random_stall.sv \
@@ -199,7 +200,7 @@ RTLSRC_VLOG_TB_TOP	:= $(basename $(notdir $(TBSRC_TOP)))
 RTLSRC_VOPT_TB_TOP	:= $(addsuffix _vopt, $(RTLSRC_VLOG_TB_TOP))
 
 TBSRC_VERI  := $(TBSRC_CORE)/tb_top_verilator.sv \
-               $(TBSRC_CORE)/cv32e40p_tb_wrapper.sv \
+               $(TBSRC_CORE)/cv32e40p_core_tb_wrapper.sv \
                $(TBSRC_CORE)/tb_riscv/riscv_rvalid_stall.sv \
                $(TBSRC_CORE)/tb_riscv/riscv_gnt_stall.sv \
                $(TBSRC_CORE)/mm_ram.sv \
@@ -276,9 +277,13 @@ mk_results:
 
 # Metrics dsim compile targets
 dsim-comp: mk_results CV_CORE_pkg tbsrc_pkg tbsrc
+	@echo "$(BANNER)"
+	@echo "* Compiling with Metrics DSIM"
+	@echo "$(BANNER)"
 		cd $(DSIM_RESULTS) && \
 		$(DSIM) \
 		$(DSIM_CMP_FLAGS) \
+		$(DSIM_SUPPRESS) \
 		$(DSIM_UVM_ARGS) \
 		-f $(CV_CORE_MANIFEST) \
 		$(TBSRC_PKG) \
@@ -287,8 +292,12 @@ dsim-comp: mk_results CV_CORE_pkg tbsrc_pkg tbsrc
 		-genimage $(DSIM_IMAGE)
 
 dsim-comp-rtl-only: mk_results $(CV_CORE_PKG)
+	@echo "$(BANNER)"
+	@echo "* Compiling (only) with Metrics DSIM"
+	@echo "$(BANNER)"
 	$(DSIM) \
 		$(DSIM_CMP_FLAGS) \
+		$(DSIM_SUPPRESS) \
 		-f $(CV_CORE_MANIFEST) \
 		-work $(DSIM_WORK) \
 		-genimage $(DSIM_IMAGE)
@@ -313,7 +322,7 @@ dsim-test: dsim-comp $(TEST_PROGRAM_PATH)/$(TEST)/$(TEST).hex
 		-work $(DSIM_WORK) \
 		$(DSIM_RUN_FLAGS) \
 		-sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so \
-		+firmware=$(VERI_CUSTOM)/$(TEST)/$(TEST).hex
+		+firmware=../../$(TEST_PROGRAM_RELPATH)/$(TEST)/$(TEST).hex
 
 # Metrics dsim cleanup
 .PHONY: dsim-clean
@@ -490,13 +499,13 @@ testbench_verilator: CV_CORE_pkg $(TBSRC_VERI) $(TBSRC_PKG)
 	@echo "$(BANNER)"
 	$(VERILATOR) --cc --sv --exe \
 		$(VERI_TRACE) \
-		--Wno-lint --Wno-UNOPTFLAT \
-		--Wno-MODDUP --top-module \
+		$(VERI_WARN_WAIVERS) \
+		--top-module \
 		tb_top_verilator $(TBSRC_VERI) \
 		-f $(CV_CORE_MANIFEST) \
 		$(CV_CORE_PKG)/bhv/$(CV_CORE_LC)_core_log.sv \
 		$(TBSRC_CORE)/tb_top_verilator.cpp --Mdir $(VERI_OBJ_DIR) \
-		-CFLAGS "-std=gnu++11 $(VERI_CFLAGS)" \
+		-CFLAGS "$(VERI_CFLAGS)" \
 		$(VERI_COMPILE_FLAGS)
 	$(MAKE) -C $(VERI_OBJ_DIR) -f Vtb_top_verilator.mk
 	mkdir -p $(SIM_RESULTS)

cv32e40p/sim/core/README.md

@@ -8,36 +8,27 @@ To run the core testbench you will need a SystemVerilog simulator and RISC-V GCC
 
 Supported SystemVerilog Simulators
 ----------------------------------
-The core testbench and associated test-programs can be run using **_Verilator_**, the Metrics
-**_dsim_**, Mentor's **_Questa_**, Cadence **_Xcelium_**, Synopsys **_vcs_** and Aldec **_Riviera-PRO_**
-simulators. Note that **_Icarus_** verilog cannot compile the RTL and there are no plans
-to support Icarus in the future.
+The core testbench and associated test-programs can be run using **_Verilator_**, Metrics
+**_DSim_**, Siemens **_Questasim_**, Cadence **_Xcelium_**, Synopsys **_vcs_** and Aldec **_Riviera-PRO_** simulators.
+Note:
+- The following has been recently tested with both Verilator and DSim, but it has been some time since other simulators have been used.  Bit-rot may have set in.
+- **_Icarus_** verilog cannot compile the RTL and there are no plans to support Icarus in the future.
 
 RISC-V GCC Compiler "Toolchain"
 -------------------------------
 Pointers to the recommended toolchain for CV32E40P are in `../TOOLCHAIN`.
 
-Running your own C programs
----------------------
-A hello world program is available and you can run it in the CV32E40P Core testbench.
-Invoke the `dsim-hello_world` or `hello-world-veri-run` makefile rules to run it with
-`dsim` or `verilator` respectively.
-
-The hello world program is located in the `custom` folder. The relevant sections
-in the Makefile on how to compile and link this program can be found under `Running
-custom programs`.  Make sure you have a working C compiler (see above) and keep in
-mind that you are running on a very basic machine.
-
 Running the testbench with [verilator](https://www.veripool.org/wiki/verilator)
 ----------------------
-Point your environment variable `RISCV` to your RISC-V toolchain. Call `make`
-to run the default test (hello_world).
+Point your environment variable `RISCV` to your RISC-V toolchain.
+Call `make` to run the default test with Verilator.
 
-Running your own Assembler programs
+Running your own C and/or RISC-V Assembler programs
 -----------------------------
 If you have a C or assembly program in `../../tests/programs/custom`
 then the following will work with Verilator:<br>
 ```
+make veri-test TEST=hello-world
 make veri-test TEST=dhrystone
 make veri-test TEST=misalign
 make veri-test TEST=fibonacci
@@ -51,6 +42,7 @@ Point your environment variable `RISCV` to your RISC-V toolchain. Call
 `make dsim-sanity` to build and run the testbench with the hello_world
 test in the custom directory. Other test targets of interest:<br>
 ```
+make dsim-test TEST=hello-world
 make dsim-test TEST=dhrystone
 make dsim-test TEST=misalign
 make dsim-test TEST=fibonacci
@@ -124,16 +116,3 @@ riviera-hello-world` to build the testbench and the firmware, and run it. Use
 `ASIM_FLAGS` to configure the simulator e.g. `make custom-asim-run
 ASIM_FLAGS="-gui"`.
 
-Options
--------
-A few plusarg options are supported:
-* `+verbose` to show all memory read and writes and other miscellaneous information.
-
-* `+vcd` to produce a vcd file called `riscy_tb.vcd`. Verilator always produces
-  a vcd file called `verilator_tb.vcd`.
-
-Examples
---------
-Run all riscv_tests to completion with **dsim**:  
-`make dsim-cv32_riscv_tests`
-

cv32e40p/tb/README.md

@@ -1,28 +1,11 @@
-## CV32/TB: testbenches for the CV32E40P CORE-V family of RISC-V cores.
-Derived from the
-[tb](https://github.com/pulp-platform/riscv/tree/master/tb)
-directory of the PULP-Platform RI5CY project.  There are two distinct
-testbenches:
+## Testbenches for the CV32E40P CORE-V family of RISC-V cores.
+There are two distinct testbenches here.
 
 ### core
-Modified to remove a few RTL files (placed these in the rtl directory). This
-testbench supports Verilator and we will do what we can to maintain Verilator
-support here.  Note that `tb_riscv` is now a sub-directory of `core`.
+A very simple testbench that can be run with Verilator and any commercial SystemVerilog simulator.
+This is not a production testbench - it is here to provide a simple example.
 
 ### uvmt
-The testbench and testharness for the CV32E40P UVM verification
-environments.  This tb/th maintains support for all features of the `core`
-testbench.  This testbench must be run with a SystemVerilog 1800-compliant simulator, 
-i.e. it cannot be run with Verilator.
-
-## Retired Testbenches
-A set of directories inherited from the RI5CY project have fallen into disuse
-and were deleted.  Since nothing is ever gone in GitHub, if you _must_ have
-this content, it is available in any hash of this repo older than
-11ffa1577abfff2f7dce8afed6047b0c86ad335c.   The deleted directories are:
-
-* dm
-* scripts
-* serDiv
-* tb_MPU
-* verilator-model
+The testbench for the CV32E40P UVM verification environment.
+This is the production environment used to verify the CV32E40P.
+This testbench must be run with a SystemVerilog 1800-compliant simulator.

cv32e40p/tb/core/cv32e40p_tb_wrapper.sv cv32e40p/tb/core/cv32e40p_core_tb_wrapper.sv

@@ -15,7 +15,7 @@
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-0.51
 
-module cv32e40p_tb_wrapper
+module cv32e40p_core_tb_wrapper
     #(parameter // Parameters used by TB
                 INSTR_RDATA_WIDTH = 32,
                 RAM_ADDR_WIDTH    = 20,
@@ -179,4 +179,4 @@ module cv32e40p_tb_wrapper
          .exit_valid_o   ( exit_valid_o                              ),
          .exit_value_o   ( exit_value_o                              ));
 
-endmodule // cv32e40p_tb_wrapper
+endmodule // cv32e40p_core_tb_wrapper

cv32e40p/tb/core/tb_top.sv

@@ -70,7 +70,7 @@ module tb_top
             if($test$plusargs("verbose"))
                 $display("[TESTBENCH] @ t=%0t: loading firmware %0s",
                          $time, firmware);
-            $readmemh(firmware, cv32e40p_tb_wrapper_i.ram_i.dp_ram_i.mem);
+            $readmemh(firmware, cv32e40p_core_tb_wrapper_i.ram_i.dp_ram_i.mem);
         end else begin
             $display("No firmware specified");
             $finish;
@@ -145,13 +145,13 @@ module tb_top
     end
 
     // wrapper for CV32E40P, the memory system and stdout peripheral
-    cv32e40p_tb_wrapper
+    cv32e40p_core_tb_wrapper
         #(
           .INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH),
           .RAM_ADDR_WIDTH    (RAM_ADDR_WIDTH),
           .BOOT_ADDR         (BOOT_ADDR)
          )
-    cv32e40p_tb_wrapper_i
+    cv32e40p_core_tb_wrapper_i
         (
          .clk_i          ( core_clk     ),
          .rst_ni         ( core_rst_n   ),

cv32e40p/tb/core/tb_top_verilator.cpp

@@ -39,7 +39,7 @@ int main(int argc, char **argv, char **env)
     top = new Vtb_top_verilator();
 
     svSetScope(svGetScopeFromName(
-        "TOP.tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i.dp_ram_i"));
+        "TOP.tb_top_verilator.cv32e40p_core_tb_wrapper_i.ram_i.dp_ram_i"));
     Verilated::scopesDump();
 
 #ifdef VCD_TRACE
@@ -56,7 +56,7 @@ int main(int argc, char **argv, char **env)
 
 #ifdef MCY
     svSetScope(svGetScopeFromName(
-        "TOP.tb_top_verilator.cv32e40p_tb_wrapper_i.riscv_core_i.ex_stage_i.alu_i.int_div.div_i"));
+        "TOP.tb_top_verilator.cv32e40p_core_tb_wrapper_i.riscv_core_i.ex_stage_i.alu_i.int_div.div_i"));
     svLogicVecVal idx = {0};
     idx.aval = mutidx;
     set_mutidx(&idx);

cv32e40p/tb/core/tb_top_verilator.sv

@@ -39,7 +39,7 @@ module tb_top_verilator
             if($test$plusargs("verbose"))
                 $display("[TESTBENCH] %t: loading firmware %0s ...",
                          $time, firmware);
-            $readmemh(firmware, cv32e40p_tb_wrapper_i.ram_i.dp_ram_i.mem);
+            $readmemh(firmware, cv32e40p_core_tb_wrapper_i.ram_i.dp_ram_i.mem);
 
         end else begin
             $display("No firmware specified");
@@ -85,7 +85,7 @@ module tb_top_verilator
     end
 
     // wrapper for cv32e40p, the memory system and stdout peripheral
-    cv32e40p_tb_wrapper
+    cv32e40p_core_tb_wrapper
         #(.INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH),
           .RAM_ADDR_WIDTH    (RAM_ADDR_WIDTH),
           .BOOT_ADDR         (BOOT_ADDR),
@@ -94,7 +94,7 @@ module tb_top_verilator
           .ZFINX             (0),
           .DM_HALTADDRESS    (32'h1A110800)
          )
-    cv32e40p_tb_wrapper_i
+    cv32e40p_core_tb_wrapper_i
         (.clk_i          ( clk_i          ),
          .rst_ni         ( rst_ni         ),
          .fetch_enable_i ( fetch_enable_i ),