Skip to content

Commit 2a5ee14

Browse files
author
pascalgouedo
authored
Merge pull request #2492 from XavierAubert/cv32e40p/illegal_script_v2
Illegal instruction generator for CV32E40Pv2
2 parents a3a121f + 11596a7 commit 2a5ee14

File tree

1 file changed

+275
-0
lines changed

1 file changed

+275
-0
lines changed

‎bin/illegal_instr_generator_cv32e40p_v2.pl

+275
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,275 @@
1+
#!/usr/bin/perl
2+
# Copyright (C) 2024 EM Microelectronic US Inc.
3+
# Copyright (C) 2024 Dolphin Design
4+
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
5+
#
6+
# illegal_instr_generator_cv32e40p_v2.pl has usage :
7+
# - “./illegal_instr_generator_cv32e40p_v2.pl <int>”
8+
# - “./illegal_instr_generator_cv32e40p_v2.pl rv32f”
9+
# - “./illegal_instr_generator_cv32e40p_v2.pl rv32Xpulp”
10+
# If first (legacy) option with int argument is selected, it produces a test approximately .
11+
# 0.64*int instructions long, where all the instructions are illegal instructions that cannot
12+
# compile or execute properly, and create a assembly file containing only illegal instructions
13+
#
14+
# The two other options 'rv32f' and 'rv32Xpulp' generates a test containing all possibly illegaly
15+
# formed instructions with all the same fixed values for operands.
16+
#
17+
# The script works by randomly or determinely generating a set of instruction encodings and then uses the
18+
# compiler to tell it if the instruction is decoded into something or assumed illegal.
19+
#
20+
# Required:
21+
# - CV_SW_TOOLCHAIN defined (path of the toolchain used, that contains the bin folder)
22+
# - CV_SW_PREFIX defined (e.g. riscv32-corev-elf-)
23+
#
24+
25+
use Data::Dumper;
26+
27+
sub test_header {
28+
return "
29+
.globl _start
30+
.globl main
31+
.globl exit
32+
.globl debug
33+
.section .text
34+
.global u_sw_irq_handler
35+
36+
37+
\#define TEST_PASS 123456789
38+
\#define TEST_FAIL 1
39+
\#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000
40+
41+
\#define EXPECTED_ILLEGAL_INSTRUCTIONS $expected_ill_number
42+
43+
main:
44+
li t0, (0x1 << 3)
45+
csrs mstatus, t0
46+
li x31, 0x0
47+
48+
\#ifdef FPU
49+
li x5, 0x00003800
50+
csrw 0x300, x5 # MSTATUS FPU enable
51+
\#endif
52+
53+
\#\#\#\#\#\#\#\#\# GENERATED CODE BELOW \#\#\#\#\#\#\#\#\#
54+
";
55+
}
56+
57+
sub test_footer {
58+
return "
59+
\#\#\#\#\#\#\#\#\# END OF GENERATED CODE \#\#\#\#\#\#\#\#\#
60+
61+
li x18, TEST_PASS
62+
li x16, EXPECTED_ILLEGAL_INSTRUCTIONS
63+
beq x31, x16, test_end
64+
li x18, TEST_FAIL
65+
66+
test_end:
67+
li x17, VIRT_PERIPH_STATUS_FLAG_ADDR
68+
sw x18,0(x17)
69+
j _exit
70+
71+
\# The \"sw_irq_handler\" is entered on each illegal instruction. Clears
72+
\# mepc and increments the illegal instruction count in x31.
73+
u_sw_irq_handler:
74+
li x30, 0xf
75+
csrrc x29, mcause, x0
76+
and x30, x29, x30
77+
li x28, 2
78+
bne x30, x28, _exit
79+
csrrc x27, mepc, x0
80+
c.addi x27, 4
81+
csrrw x0, mepc, x27
82+
c.addi x31, 1
83+
mret
84+
85+
_exit:
86+
j _exit
87+
88+
debug:
89+
j _exit
90+
91+
";
92+
}
93+
94+
# to simplify generation and make sure every illegal are reached for F extension, the generation is retricted to a small set of opcodes, and fixed values for rs1 and rd
95+
sub F_gen {
96+
open OUT_FILE, '>', "illegal_instr_temp.S" or die "Can't open illegal_instr_temp.S";
97+
98+
print OUT_FILE ".section .init\n";
99+
print OUT_FILE ".global _start\n";
100+
print OUT_FILE "_start:\n";
101+
102+
my @rd_opcode_list = ( "287", "2a7", "2c3", "2c7", "2cb", "2cf", "2d3");
103+
my @rs1_func3_list = ( "50" .. "57" );
104+
my @func7_rs2_list = ( 0x000 .. 0xfff );
105+
106+
my @func7_rs2_maddsub = ( "525", "545", "565" );
107+
my $rs1_func3_maddsub = "55";
108+
109+
my $func7_rs2_load_store = "aaa";
110+
111+
# FLW & FSW (h287 & h2A7) ony rm != 010 (rs1_rd not )should be generated, with fixed values for others.
112+
113+
foreach my $opcode ( @rd_opcode_list ) {
114+
if ( $opcode =~ /^2c/) { # f[n]madd/sub
115+
foreach my $itr ( @func7_rs2_maddsub ) {
116+
print OUT_FILE (".word(0x" . $itr . $rs1_func3_maddsub . $opcode . ")\n");
117+
}
118+
} elsif ( $opcode eq "287" or $opcode eq "2a7" ) { # FLW / FSW
119+
foreach my $itr ( @rs1_func3_list ) {
120+
print OUT_FILE (".word(0x" . $func7_rs2_load_store . $itr . $opcode . ")\n");
121+
}
122+
} else { # every other F options
123+
foreach my $func7_rs2 ( @func7_rs2_list ) {
124+
foreach my $itr ( @rs1_func3_list ) {
125+
print OUT_FILE (".word(0x" . sprintf("%03x", $func7_rs2) . $itr . $opcode . ")\n");
126+
}
127+
}
128+
}
129+
}
130+
131+
close OUT_FILE;
132+
}
133+
134+
sub Xpulp_gen {
135+
open OUT_FILE, '>', "illegal_instr_temp.S" or die "Can't open illegal_instr_temp.S";
136+
137+
print OUT_FILE ".section .init\n";
138+
print OUT_FILE ".global _start\n";
139+
print OUT_FILE "_start:\n";
140+
141+
my @func7_list = ( 0x00 .. 0xff );
142+
my @func4_list = ( 0x0 .. 0xf );
143+
144+
# for Custom-0, only cv.elw can be illegal instruction if CLUSTER is not present
145+
print OUT_FILE (".word(0x5555350b)\n");
146+
147+
# for Custom-1, three func3 values are illegal :
148+
print OUT_FILE (".word(0xaaa5552b)\n");
149+
print OUT_FILE (".word(0xaaa5652b)\n");
150+
print OUT_FILE (".word(0xaaa5752b)\n");
151+
152+
# for func3 = 011 :
153+
my $custom1_rs2_rs1_func3 = "a53";
154+
my $custom1_opcode = "52b";
155+
156+
# iteration are done below together with custom-3
157+
158+
# for func3 = 100
159+
# bits [7:0] are either AB or 2B, func3 is fixed, and uimmL rs1 should not be zero
160+
my $custom1_rs1_func3 = "54";
161+
my $uimml = "555";
162+
foreach (@func4_list) {
163+
print OUT_FILE (".word(0x". $uimml . $custom1_rs1_func3 . sprintf("%01x", $_) . "2b" . ")\n");
164+
print OUT_FILE (".word(0x". $uimml . $custom1_rs1_func3 . sprintf("%01x", $_) . "ab" . ")\n");
165+
}
166+
167+
# custom-2
168+
# for custom-2 three cases of illegal f2,func3 = {11,000} or {10,001}; f2,func3 = {11,001} & Is[4:2] != 0
169+
print OUT_FILE (".word(0xcaa5055b)\n");
170+
print OUT_FILE (".word(0x8aa5155b)\n");
171+
print OUT_FILE (".word(0xcaa5155b)\n");
172+
173+
# custom-3
174+
my $custom3_opcode = "57b";
175+
my @custom3_rs2_rs1_func3_list = ( "a50" .. "a57" );
176+
177+
# iteration for custom1 func3 011 & custom3
178+
foreach my $f7 (@func7_list) {
179+
print OUT_FILE (".word(0x". sprintf("%02x", $f7) . $custom1_rs2_rs1_func3 . $custom1_opcode . ")\n");
180+
foreach my $c3 (@custom3_rs2_rs1_func3_list) {
181+
print OUT_FILE (".word(0x". sprintf("%02x", $f7) . $c3 . $custom3_opcode . ")\n");
182+
}
183+
}
184+
185+
close OUT_FILE;
186+
}
187+
188+
sub all_gen_rand {
189+
my $nb_instr = $_[0];
190+
191+
open OUT_FILE, '>', "illegal_instr_temp.S" or die "Can't open illegal_instr_temp.S";
192+
193+
print OUT_FILE ".section .init\n";
194+
print OUT_FILE ".global _start\n";
195+
print OUT_FILE "_start:\n";
196+
197+
my @set = ('0' .. '9', 'a' .. 'f');
198+
for ($i = 0; $i<$nb_instr; $i++){
199+
$str = join '' => map $set[rand @set], 1 .. 8;
200+
$str = (".word(0x" . $str . ")");
201+
print OUT_FILE ("$str\n");
202+
}
203+
close OUT_FILE;
204+
}
205+
206+
my $march = "rv32imc_zicsr";
207+
208+
# gen using rand method as before
209+
if ($ARGV[0] eq "rv32f" ) {
210+
F_gen();
211+
$march = "rv32imfc";
212+
} elsif ($ARGV[0] eq "rv32Xpulp" ) {
213+
Xpulp_gen();
214+
$march = "rv32imc_zicsr_zifencei_xcvhwlp1p0_xcvmem1p0_xcvmac1p0_xcvbi1p0_xcvalu1p0_xcvsimd1p0_xcvbitmanip1p0";
215+
} else {
216+
all_gen_rand($ARGV[0]);
217+
}
218+
219+
$cmd = ("-Os -g -D__riscv__=1 -D__LITTLE_ENDIAN__=1 -march=$march -Wa,-march=$march -fdata-sections -ffunction-sections -fdiagnostics-color=always");
220+
#print ("Compiling list of interrupted instructions (interrupted_instructions.S) into an object file (interrupted_instructions.o)\n");
221+
print "$ENV{CV_SW_TOOLCHAIN}/bin/$ENV{CV_SW_PREFIX}gcc ${cmd} -o illegal_instr_temp.o -c illegal_instr_temp.S\n";
222+
`$ENV{CV_SW_TOOLCHAIN}/bin/$ENV{CV_SW_PREFIX}gcc ${cmd} -o illegal_instr_temp.o -c illegal_instr_temp.S`;
223+
#print ("Compiling list of objects (interrupted_instructions.o) into an objdump file (interrupted_instructions.objdump)\n");
224+
`$ENV{CV_SW_TOOLCHAIN}/bin/$ENV{CV_SW_PREFIX}objdump -D --disassemble=_start illegal_instr_temp.o > illegal_instr_temp.objdump`;
225+
226+
open my $fh, '<', "illegal_instr_temp.objdump" or die "Can't open illegal_instr_temp.S";
227+
228+
if ($ARGV[0] ne "rv32f" and $ARGV[0] ne "rv32Xpulp") {
229+
while(<$fh>){
230+
chomp;
231+
s/^\s+//;
232+
@fields = split(/\s+/);
233+
if ( $fields[0] =~ /^[a-f0-9]+\:/ and ($fields[2] eq ".insn" or $fields[3] =~ /unknown/) ) {
234+
$str = ".word(0x" . $fields[1] . ")";
235+
$illegal_instr{$str} = 1;
236+
}
237+
}
238+
} else {
239+
while(<$fh>){
240+
chomp;
241+
s/^\s+//;
242+
@fields = split(/\s+/);
243+
if ( $fields[0] =~ /^[a-f0-9]+\:/ and ($fields[2] eq ".insn" or $fields[3] =~ /unknown/) ) {
244+
$str = ".word(0x" . $fields[1] . ")";
245+
$illegal_instr{$str} = 1;
246+
}
247+
}
248+
}
249+
250+
our $expected_ill_number = scalar keys %illegal_instr;
251+
252+
close $fh;
253+
open my $fh, '<', "illegal_instr_temp.S" or die "Can't open illegal_instr_temp.S for parsing";
254+
open OUT_FILE, '>', "illegal_instr_test.S" or die "Can't open illegal_instr_test.S";
255+
256+
print ($expected_ill_number . " illegal instructions generated\n");
257+
258+
print OUT_FILE test_header();
259+
260+
while(<$fh>){
261+
chomp;
262+
$comp_string = $_;
263+
if(exists($illegal_instr{$comp_string})){
264+
print OUT_FILE " "x4 . "$comp_string\n";
265+
}
266+
}
267+
close $fh;
268+
269+
print OUT_FILE test_footer();
270+
271+
close OUT_FILE;
272+
273+
`$ENV{CV_SW_TOOLCHAIN}/bin/$ENV{CV_SW_PREFIX}gcc ${cmd} -o illegal_instr_test.o -c illegal_instr_test.S`;
274+
`$ENV{CV_SW_TOOLCHAIN}/bin/$ENV{CV_SW_PREFIX}objdump -xd illegal_instr_test.o > illegal_instr_test.objdump`;
275+
`rm -f illegal_instr_temp.o illegal_instr_temp.objdump illegal_instr_temp.S illegal_instr_test.o`;

0 commit comments

Comments
 (0)