Typos cleanup.

Signed-off-by: Pascal Gouedo <[email protected]>

Author: Pascal Gouedo

cv32e40p/docs/VerifPlans/README.md

@@ -8,7 +8,7 @@ Below are two different chapters describing verification plans status and direct
 # CV32E40P (V2) Verification Plans
 
 ## Short verification methodology introduction
-For CV32E40P**v2** verification, the formal verification methodology has been choosen over the stimuli-based simulation that was done for version one of the core. However, full verification closure is not feasible using only formal verification due to complexity of specific scenarios. All these specific uncoverable scenarios from formal verification are then exercised by stimuli-based simulation using a reference model of the core. These scenarios along with formal assertions are described inside verifications plans, for which details are given in a table below. Regarding already available v1 plans, their re-use or not is specified in this table.
+For CV32E40Pv2 verification, the formal verification methodology has been chosen over the stimuli-based simulation that was done for v1 version of the core. However, full verification closure is not feasible using only formal verification due to complexity of specific scenarios. All these specific uncoverable scenarios from formal verification are then exercised by stimuli-based simulation using a reference model of the core. These scenarios along with formal assertions are described inside verifications plans, for which details are given in a table below. Regarding already available v1 plans, their re-use or not is specified in this table.
 
 ## Verification Plan Status
 
@@ -34,7 +34,7 @@ Under the heading `Link`, the name shown corresponds to the filename of the vpla
 | **Debug & Trace**   | Debug          | v1-reused | Reviewed | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")|
 | **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
 | **Micro-architecture** | OBI |  v1-reused  | Reviewed |         | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") |
-|                        | Pipeline / SleepUnit | v1-reused | Reviewed |  | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") |
+|                        | Pipeline / Sleep Unit | v1-reused | Reviewed |  | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") |
 |                        | FPU Register File | v2-sim-new | Reviewed |  | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") |
 | **Additional ISA** | F / Zfinx | v2-sim-new | Reviewed | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") |
 | **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |