Add CVA6 performance model (#2880)

Author: cathales

README.md

@@ -4,6 +4,9 @@ CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V
 
 It has a configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.
 
+A performance model of CVA6 is available in the `perf-model/` folder of this repository.
+It can be used to investigate performance-related micro-architecture changes.
+
 <img src="docs/03_cva6_design/_static/ariane_overview.drawio.png"/>
 
 

perf-model/README.md

@@ -0,0 +1,79 @@
+# CVA6 cycle-accurate performance model
+
+This repository contains a cycle-accurate performance model of CVA6 control-path.
+
+It was developed to explore microarchitecture changes in CVA6 before implementing them.
+
+To cite this model, please head to the end of this document.
+
+
+## Getting started
+
+### Adapt RVFI trace generation
+
+The regular expression expects the cycle number to be in the RVFI trace.
+The value is not used by the model but it is used to compare the model and CVA6.
+
+To emit cycle number in RVFI trace, modify `corev_apu/tb/rvfi_tracer.sv` in CVA6 repository as below.
+
+```diff
+-        $fwrite(f, "core   0: 0x%h (0x%h) DASM(%h)\n",
+-          pc64, rvfi_i[i].insn, rvfi_i[i].insn);
++        $fwrite(f, "core   0: 0x%h (0x%h) @%d DASM(%h)\n",
++          pc64, rvfi_i[i].insn, cycles, rvfi_i[i].insn);
+```
+
+
+### Generate an RVFI trace
+
+To generate an RVFI trace, follow the instructions in the CVA6 repository to run a simulation.
+The RVFI trace will be in `verif/sim/out_<date>/<simulator>/<test-name>.log`.
+
+
+### Running the model
+
+```bash
+python3 model.py verif/sim/out_<date>/<simulator>/<test-name>.log
+```
+
+
+### Exploring design space
+
+In `model.py`, the `main` function runs the model with arguments which override default values.
+Generic parameters are available in `Model.__init__`.
+You can add new parameters to explore here.
+
+To perform exploration, run the model in a loop, like `issue_commit_graph` does.
+The `display_scores` function is meant to print a 3D plot if you have `matplotlib`.
+`issue_commit_graph` prints the scores so that you can store it and display the figure without re-running the model.
+
+
+## Files
+
+| Name            | Description                                              |
+| :---            | :---                                                     |
+| `cycle_diff.py` | Calculates duration of each instruction in an RVFI trace |
+| `isa.py`        | Module to create Python objects from RISC-V instructions |
+| `model.py`      | The CVA6 performance model                               |
+
+
+## Citing
+
+```bibtex
+@inproceedings{cf24,
+   author = {Allart, C\^{o}me and Coulon, Jean-Roch and Sintzoff, Andr\'{e} and Potin, Olivier and Rigaud, Jean-Baptiste},
+   title = {Using a Performance Model to Implement a Superscalar CVA6},
+   year = {2024},
+   isbn = {9798400704925},
+   publisher = {Association for Computing Machinery},
+   url = {https://doi.org/10.1145/3637543.3652871},
+   doi = {10.1145/3637543.3652871},
+   abstract = {A performance model of CVA6 RISC-V processor is built to evaluate performance-related modifications before implementing them in RTL. Its accuracy is 99.2\% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40\% on CoreMark.},
+   booktitle = {Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions},
+   pages = {43–46},
+   numpages = {4},
+   keywords = {CVA6, Cycle-Based Model, Multi-Issue, Performance, RISC-V, Superscalar},
+   location = {Ischia, Italy},
+   series = {CF '24 Companion}
+}
+```

perf-model/cycle_diff.py

@@ -0,0 +1,80 @@
+# Copyright 2024 Thales Silicon Security
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Côme ALLART - Thales
+
+import re
+import sys
+
+re_csrr_minstret = re.compile(r"^csrr\s+\w+,\s*minstret$")
+re_full = re.compile(
+    r"([a-z]+)\s+0:\s*0x00000000([0-9a-f]+)\s*\(([0-9a-fx]+)\)\s*(\S*)@\s*([0-9]+)\s*(.*)"
+)
+
+class Trace:
+    def __init__(self, addr, cycle, mnemo, flags):
+        self.addr = addr
+        self.cycle = cycle
+        self.mnemo = mnemo
+        self.flags = flags
+        self.delta = None
+
+    def report(self):
+        """True if the instruction is a loading instruction"""
+        return f"+{self.delta} {self.flags} 0x{self.addr}: {self.mnemo}"
+
+def print_data(name, value):
+    "Prints 'name = data' with alignment of the '='"
+    spaces = ' ' * (24 - len(name))
+    print(f"{name}{spaces} = {value}")
+
+def read_traces(input_file):
+    "Collect stage traces from file"
+    l = []
+    def filter_add(trace):
+        if not hasattr(filter_add, "accepting"):
+            filter_add.accepting = False
+        if re_csrr_minstret.search(trace.mnemo):
+            filter_add.accepting = not filter_add.accepting
+            return
+        if filter_add.accepting:
+            l.append(trace)
+    with open(input_file, "r", encoding="utf8") as f:
+        for line in [l.strip() for l in f]:
+            found = re_full.search(line)
+            if found:
+                addr = found.group(2)
+                flags = found.group(4)
+                cycle = int(found.group(5))
+                mnemo = found.group(6)
+                filter_add(Trace(addr, cycle, mnemo, flags))
+                #l.append(Trace(addr, cycle, mnemo, flags))
+    return l
+
+def write_traces(outfile, traces):
+    "Write all instructions to output file"
+    print("output file:", outfile)
+    with open(outfile, "w", encoding="utf8") as f:
+        for trace in traces:
+            f.write(trace.report() + "\n")
+
+def main(input_file: str):
+    "Main function"
+    traces = read_traces(input_file)
+    cycle = traces[0].cycle
+    cycle_number = traces[-1].cycle - cycle + 1
+    for trace in traces:
+        trace.delta = trace.cycle - cycle
+        cycle = trace.cycle
+    print_data("cycle number", cycle_number)
+    print_data("Coremark/MHz", 1000000 / cycle_number)
+    print_data("instruction number", len(traces))
+    print_data("IPC", len(traces) / cycle_number)
+    write_traces("traceout.log", traces)
+
+if __name__ == "__main__":
+    main(sys.argv[1])