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David BriemannSendaoYan
David Briemann
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SendaoYan
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8357304: [PPC64] C2: Implement MinV, MaxV and Reduction nodes
Reviewed-by: mdoerr, varadam
1 parent c62223a commit 061b24d

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‎src/hotspot/cpu/ppc/assembler_ppc.hpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -591,6 +591,10 @@ class Assembler : public AbstractAssembler {
591591
XVRDPIC_OPCODE = (60u << OPCODE_SHIFT | 235u << 2),
592592
XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2),
593593
XVRDPIP_OPCODE = (60u << OPCODE_SHIFT | 233u << 2),
594+
XVMINSP_OPCODE = (60u << OPCODE_SHIFT | 200u << 3),
595+
XVMINDP_OPCODE = (60u << OPCODE_SHIFT | 232u << 3),
596+
XVMAXSP_OPCODE = (60u << OPCODE_SHIFT | 192u << 3),
597+
XVMAXDP_OPCODE = (60u << OPCODE_SHIFT | 224u << 3),
594598

595599
// Deliver A Random Number (introduced with POWER9)
596600
DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1),
@@ -699,15 +703,19 @@ class Assembler : public AbstractAssembler {
699703
VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
700704
VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
701705
VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
706+
VMAXSD_OPCODE = (4u << OPCODE_SHIFT | 450u ),
702707
VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
703708
VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
704709
VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
710+
VMAXUD_OPCODE = (4u << OPCODE_SHIFT | 194u ),
705711
VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
706712
VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
707713
VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
714+
VMINSD_OPCODE = (4u << OPCODE_SHIFT | 962u ),
708715
VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
709716
VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
710717
VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
718+
VMINUD_OPCODE = (4u << OPCODE_SHIFT | 706u ),
711719

712720
VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
713721
VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
@@ -2302,15 +2310,19 @@ class Assembler : public AbstractAssembler {
23022310
inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
23032311
inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
23042312
inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
2313+
inline void vmaxsd( VectorRegister d, VectorRegister a, VectorRegister b);
23052314
inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
23062315
inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
23072316
inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
2317+
inline void vmaxud( VectorRegister d, VectorRegister a, VectorRegister b);
23082318
inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
23092319
inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
23102320
inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
2321+
inline void vminsd( VectorRegister d, VectorRegister a, VectorRegister b);
23112322
inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
23122323
inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
23132324
inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
2325+
inline void vminud( VectorRegister d, VectorRegister a, VectorRegister b);
23142326
inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
23152327
inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
23162328
inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
@@ -2435,6 +2447,12 @@ class Assembler : public AbstractAssembler {
24352447
inline void xvrdpim( VectorSRegister d, VectorSRegister b);
24362448
inline void xvrdpip( VectorSRegister d, VectorSRegister b);
24372449

2450+
// The following functions do not match exactly the Java.math semantics.
2451+
inline void xvminsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2452+
inline void xvmindp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2453+
inline void xvmaxsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2454+
inline void xvmaxdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2455+
24382456
// VSX Extended Mnemonics
24392457
inline void xxspltd( VectorSRegister d, VectorSRegister a, int x);
24402458
inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b);

‎src/hotspot/cpu/ppc/assembler_ppc.inline.hpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -908,6 +908,11 @@ inline void Assembler::xvrdpic( VectorSRegister d, VectorSRegister b)
908908
inline void Assembler::xvrdpim( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIM_OPCODE | vsrt(d) | vsrb(b)); }
909909
inline void Assembler::xvrdpip( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIP_OPCODE | vsrt(d) | vsrb(b)); }
910910

911+
inline void Assembler::xvminsp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMINSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
912+
inline void Assembler::xvmindp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMINDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
913+
inline void Assembler::xvmaxsp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMAXSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
914+
inline void Assembler::xvmaxdp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMAXDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
915+
911916
inline void Assembler::mtvrd( VectorRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
912917
inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
913918
inline void Assembler::mtvrwz( VectorRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
@@ -1022,15 +1027,19 @@ inline void Assembler::vavguh( VectorRegister d, VectorRegister a, VectorRegist
10221027
inline void Assembler::vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10231028
inline void Assembler::vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10241029
inline void Assembler::vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
1030+
inline void Assembler::vmaxsd( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXSD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10251031
inline void Assembler::vmaxub( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10261032
inline void Assembler::vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10271033
inline void Assembler::vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
1034+
inline void Assembler::vmaxud( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMAXUD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10281035
inline void Assembler::vminsb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10291036
inline void Assembler::vminsw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10301037
inline void Assembler::vminsh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
1038+
inline void Assembler::vminsd( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINSD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10311039
inline void Assembler::vminub( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10321040
inline void Assembler::vminuw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10331041
inline void Assembler::vminuh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
1042+
inline void Assembler::vminud( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VMINUD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10341043
inline void Assembler::vcmpequb(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
10351044
inline void Assembler::vcmpequh(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }
10361045
inline void Assembler::vcmpequw(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCMPEQUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(0)); }

‎src/hotspot/cpu/ppc/c2_MacroAssembler_ppc.cpp

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -619,3 +619,48 @@ void C2_MacroAssembler::count_positives(Register src, Register cnt, Register res
619619
bind(Ldone);
620620
subf(result, src, result); // Result is offset from src.
621621
}
622+
623+
void C2_MacroAssembler::reduceI(int opcode, Register dst, Register iSrc, VectorRegister vSrc,
624+
VectorRegister vTmp1, VectorRegister vTmp2) {
625+
626+
auto fn_vec_op = [this](int opcode, const VectorRegister &dst, const VectorRegister &a, const VectorRegister &b) {
627+
switch(opcode) {
628+
case Op_AddReductionVI: vadduwm(dst, a, b); break;
629+
case Op_MulReductionVI: vmuluwm(dst, a , b); break;
630+
case Op_AndReductionV: vand(dst, a, b); break;
631+
case Op_OrReductionV: vor(dst, a, b); break;
632+
case Op_XorReductionV: vxor(dst, a, b); break;
633+
case Op_MinReductionV: vminsw(dst, a, b); break;
634+
case Op_MaxReductionV: vmaxsw(dst, a, b); break;
635+
default: assert(false, "wrong opcode");
636+
}
637+
};
638+
639+
auto fn_scalar_op = [this](int opcode, const Register &dst, const Register &a, const Register &b) {
640+
switch (opcode) {
641+
case Op_AddReductionVI: add(dst, a, b); break;
642+
case Op_MulReductionVI: mullw(dst, a, b); break;
643+
case Op_AndReductionV: andr(dst, a, b); break;
644+
case Op_OrReductionV: orr(dst, a, b); break;
645+
case Op_XorReductionV: xorr(dst, a, b); break;
646+
case Op_MinReductionV:
647+
cmpw(CR0, a, b);
648+
isel(dst, CR0, Assembler::less, /*invert*/false, a, b);
649+
break;
650+
case Op_MaxReductionV:
651+
cmpw(CR0, a, b);
652+
isel(dst, CR0, Assembler::greater, /*invert*/false, a, b);
653+
break;
654+
default: assert(false, "wrong opcode");
655+
}
656+
};
657+
658+
// vSrc = [i0,i1,i2,i3]
659+
vsldoi(vTmp1, vSrc, vSrc, 8); // vTmp1 <- [i2,i3,i0,i1]
660+
fn_vec_op(opcode, vTmp2, vSrc, vTmp1); // vTmp2 <- [op(i0,i2), op(i1,i3), op(i2,i0), op(i3,i1)]
661+
vsldoi(vTmp1, vTmp2, vTmp2, 4); // vTmp1 <- [op(i1,i3), op(i2,i0), op(i3,i1), op(i0,i2)]
662+
fn_vec_op(opcode, vTmp1, vTmp1, vTmp2); // vTmp1 <- [op(i0,i1,i2,i3), op(i0,i1,i2,i3), op(i0,i1,i2,i3), op(i0,i1,i2,i3)]
663+
mfvsrwz(R0, vTmp1.to_vsr()); // R0 <- op(i0,i1,i2,i3)
664+
fn_scalar_op(opcode, dst, iSrc, R0); // dst <- op(iSrc, R0)
665+
}
666+

‎src/hotspot/cpu/ppc/c2_MacroAssembler_ppc.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,4 +73,6 @@
7373

7474
void count_positives(Register src, Register cnt, Register result, Register tmp1, Register tmp2);
7575

76+
void reduceI(int opcode, Register dst, Register iSrc, VectorRegister vSrc, VectorRegister vTmp1, VectorRegister vTmp2);
77+
7678
#endif // CPU_PPC_C2_MACROASSEMBLER_PPC_HPP

‎src/hotspot/cpu/ppc/ppc.ad

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2399,6 +2399,18 @@ bool Matcher::match_rule_supported(int opcode) {
23992399
case Op_SubVL:
24002400
case Op_MulVI:
24012401
case Op_RoundDoubleModeV:
2402+
case Op_MinV:
2403+
case Op_MaxV:
2404+
case Op_AndV:
2405+
case Op_OrV:
2406+
case Op_XorV:
2407+
case Op_AddReductionVI:
2408+
case Op_MulReductionVI:
2409+
case Op_AndReductionV:
2410+
case Op_OrReductionV:
2411+
case Op_XorReductionV:
2412+
case Op_MinReductionV:
2413+
case Op_MaxReductionV:
24022414
return SuperwordUseVSX;
24032415
case Op_PopCountVI:
24042416
case Op_PopCountVL:
@@ -2440,6 +2452,22 @@ bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
24402452
if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
24412453
return false;
24422454
}
2455+
// Special cases
2456+
switch (opcode) {
2457+
// Reductions only support INT at the moment.
2458+
case Op_AddReductionVI:
2459+
case Op_MulReductionVI:
2460+
case Op_AndReductionV:
2461+
case Op_OrReductionV:
2462+
case Op_XorReductionV:
2463+
case Op_MinReductionV:
2464+
case Op_MaxReductionV:
2465+
return bt == T_INT;
2466+
// MaxV, MinV need types == INT || LONG.
2467+
case Op_MaxV:
2468+
case Op_MinV:
2469+
return bt == T_INT || bt == T_LONG;
2470+
}
24432471
return true; // Per default match rules are supported.
24442472
}
24452473

@@ -13485,6 +13513,113 @@ instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
1348513513
ins_pipe(pipe_class_default);
1348613514
%}
1348713515

13516+
// Vector Min / Max Instructions
13517+
13518+
instruct vmin_reg(vecX dst, vecX src1, vecX src2) %{
13519+
match(Set dst (MinV src1 src2));
13520+
format %{ "VMIN $dst,$src1,$src2\t// vector min" %}
13521+
size(4);
13522+
ins_encode %{
13523+
BasicType bt = Matcher::vector_element_basic_type(this);
13524+
switch (bt) {
13525+
case T_INT:
13526+
__ vminsw($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13527+
break;
13528+
case T_LONG:
13529+
__ vminsd($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13530+
break;
13531+
default:
13532+
ShouldNotReachHere();
13533+
}
13534+
%}
13535+
ins_pipe(pipe_class_default);
13536+
%}
13537+
13538+
instruct vmax_reg(vecX dst, vecX src1, vecX src2) %{
13539+
match(Set dst (MaxV src1 src2));
13540+
format %{ "VMAX $dst,$src1,$src2\t// vector max" %}
13541+
size(4);
13542+
ins_encode %{
13543+
BasicType bt = Matcher::vector_element_basic_type(this);
13544+
switch (bt) {
13545+
case T_INT:
13546+
__ vmaxsw($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13547+
break;
13548+
case T_LONG:
13549+
__ vmaxsd($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13550+
break;
13551+
default:
13552+
ShouldNotReachHere();
13553+
}
13554+
%}
13555+
ins_pipe(pipe_class_default);
13556+
%}
13557+
13558+
instruct vand(vecX dst, vecX src1, vecX src2) %{
13559+
match(Set dst (AndV src1 src2));
13560+
size(4);
13561+
format %{ "VAND $dst,$src1,$src2\t// and vectors" %}
13562+
ins_encode %{
13563+
__ vand($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13564+
%}
13565+
ins_pipe(pipe_class_default);
13566+
%}
13567+
13568+
instruct vor(vecX dst, vecX src1, vecX src2) %{
13569+
match(Set dst (OrV src1 src2));
13570+
size(4);
13571+
format %{ "VOR $dst,$src1,$src2\t// or vectors" %}
13572+
ins_encode %{
13573+
__ vor($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13574+
%}
13575+
ins_pipe(pipe_class_default);
13576+
%}
13577+
13578+
instruct vxor(vecX dst, vecX src1, vecX src2) %{
13579+
match(Set dst (XorV src1 src2));
13580+
size(4);
13581+
format %{ "VXOR $dst,$src1,$src2\t// xor vectors" %}
13582+
ins_encode %{
13583+
__ vxor($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
13584+
%}
13585+
ins_pipe(pipe_class_default);
13586+
%}
13587+
13588+
instruct reductionI_arith_logic(iRegIdst dst, iRegIsrc srcInt, vecX srcVec, vecX tmp1, vecX tmp2) %{
13589+
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_INT);
13590+
match(Set dst (AddReductionVI srcInt srcVec));
13591+
match(Set dst (MulReductionVI srcInt srcVec));
13592+
match(Set dst (AndReductionV srcInt srcVec));
13593+
match(Set dst ( OrReductionV srcInt srcVec));
13594+
match(Set dst (XorReductionV srcInt srcVec));
13595+
effect(TEMP tmp1, TEMP tmp2);
13596+
ins_cost(DEFAULT_COST * 6);
13597+
format %{ "REDUCEI_ARITH_LOGIC // $dst,$srcInt,$srcVec,$tmp1,$tmp2\t// reduce vector int add/mul/and/or/xor" %}
13598+
size(24);
13599+
ins_encode %{
13600+
int opcode = this->ideal_Opcode();
13601+
__ reduceI(opcode, $dst$$Register, $srcInt$$Register, $srcVec$$VectorSRegister->to_vr(),
13602+
$tmp1$$VectorSRegister->to_vr(), $tmp2$$VectorSRegister->to_vr());
13603+
%}
13604+
ins_pipe(pipe_class_default);
13605+
%}
13606+
13607+
instruct reductionI_min_max(iRegIdst dst, iRegIsrc srcInt, vecX srcVec, vecX tmp1, vecX tmp2, flagsRegCR0 cr0) %{
13608+
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_INT);
13609+
match(Set dst (MinReductionV srcInt srcVec));
13610+
match(Set dst (MaxReductionV srcInt srcVec));
13611+
effect(TEMP tmp1, TEMP tmp2, KILL cr0);
13612+
ins_cost(DEFAULT_COST * 7);
13613+
format %{ "REDUCEI_MINMAX // $dst,$srcInt,$srcVec,$tmp1,$tmp2,cr0\t// reduce vector int min/max" %}
13614+
size(28);
13615+
ins_encode %{
13616+
int opcode = this->ideal_Opcode();
13617+
__ reduceI(opcode, $dst$$Register, $srcInt$$Register, $srcVec$$VectorSRegister->to_vr(),
13618+
$tmp1$$VectorSRegister->to_vr(), $tmp2$$VectorSRegister->to_vr());
13619+
%}
13620+
ins_pipe(pipe_class_default);
13621+
%}
13622+
1348813623
// Vector Absolute Instructions
1348913624

1349013625
instruct vabs4F_reg(vecX dst, vecX src) %{

‎test/hotspot/jtreg/compiler/loopopts/superword/MinMaxRed_Int.java

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,8 @@ public static void ReductionInit(int[] a, int[] b) {
9696
@IR(applyIfPlatform = {"riscv64", "true"},
9797
applyIfCPUFeature = {"rvv", "true"},
9898
counts = {IRNode.MIN_REDUCTION_V, " > 0"})
99+
@IR(applyIfPlatform = {"ppc", "true"},
100+
counts = {IRNode.MIN_REDUCTION_V, " > 0"})
99101
public static int minReductionImplement(int[] a, int[] b, int res) {
100102
for (int i = 0; i < a.length; i++) {
101103
res = Math.min(res, a[i] * b[i]);
@@ -110,6 +112,8 @@ public static int minReductionImplement(int[] a, int[] b, int res) {
110112
@IR(applyIfPlatform = {"riscv64", "true"},
111113
applyIfCPUFeature = {"rvv", "true"},
112114
counts = {IRNode.MAX_REDUCTION_V, " > 0"})
115+
@IR(applyIfPlatform = {"ppc", "true"},
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counts = {IRNode.MAX_REDUCTION_V, " > 0"})
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public static int maxReductionImplement(int[] a, int[] b, int res) {
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for (int i = 0; i < a.length; i++) {
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res = Math.max(res, a[i] * b[i]);

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