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zephyr: update to 20250520
Adds missing cmsis_6 submodule, fixes the DCMI overlay and shield name.
1 parent 69ae9ba commit 899a945

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4 files changed

+11
-11
lines changed

4 files changed

+11
-11
lines changed

boards.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ giga.menu.debug.false.postbuild_debug=
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giga.menu.debug.true.postbuild_debug=-debug
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giga.build.zephyr_target=arduino_giga_r1//m7
16-
giga.build.zephyr_args=--shield giga_display_shield
16+
giga.build.zephyr_args=--shield arduino_giga_display_shield
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giga.build.variant=arduino_giga_r1_stm32h747xx_m7
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giga.build.mcu=cortex-m7
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giga.build.fpu=-mfpu=fpv5-d16

loader/llext_exports.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,6 @@ FORCE_EXPORT_SYM(net_mgmt_NET_REQUEST_WIFI_AP_ENABLE);
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113113
#if defined(CONFIG_BT)
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FORCE_EXPORT_SYM(bt_enable_raw);
115-
FORCE_EXPORT_SYM(bt_hci_raw_set_mode);
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FORCE_EXPORT_SYM(bt_send);
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FORCE_EXPORT_SYM(bt_buf_get_tx);
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FORCE_EXPORT_SYM(net_buf_simple_pull);

variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.overlay

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -148,24 +148,22 @@
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&dcmi {
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status = "okay";
151-
sensor = <&gc2145>;
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/* ext-sdram = <&sdram1>; */
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pinctrl-0 = <&dcmi_hsync_ph8 &dcmi_pixclk_pa6 &dcmi_vsync_pi5
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&dcmi_d0_ph9 &dcmi_d1_ph10 &dcmi_d2_ph11 &dcmi_d3_pg11
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&dcmi_d4_ph14 &dcmi_d5_pi4 &dcmi_d6_pi6 &dcmi_d7_pi7>;
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pinctrl-names = "default";
157-
bus-width = <8>;
158-
hsync-active = <0>;
159-
vsync-active = <0>;
160-
pixelclk-active = <0>;
161-
capture-rate = <1>;
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dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
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STM32_DMA_MEM_INC | STM32_DMA_PERIPH_32BITS | STM32_DMA_MEM_32BITS |
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STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>;
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port {
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dcmi_ep_in: endpoint {
168-
remote-endpoint = <&gc2145_ep_out>;
162+
remote-endpoint-label = "gc2145_ep_out";
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bus-width = <8>;
164+
hsync-active = <0>;
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vsync-active = <0>;
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pclk-sample = <0>;
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};
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};
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};

west.yml

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,14 +15,17 @@ manifest:
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url-base: https://github.com/arduino
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- name: facchinm
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url-base: https://github.com/facchinm
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- name: pillo79
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url-base: https://github.com/pillo79
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projects:
2022
- name: zephyr
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remote: arduino
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revision: arduino_core_merge_post_4.1
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remote: pillo79
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revision: zephyr-arduino-20250520
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import:
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name-allowlist:
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- cmsis
28+
- cmsis_6
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- hal_nordic
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- hal_ti
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- hal_ambiq

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