Skip to content

Commit 43aa0df

Browse files
committed
cache layouts
1 parent 0c96eb2 commit 43aa0df

File tree

1 file changed

+7
-5
lines changed

1 file changed

+7
-5
lines changed

Diff for: InternalDocs/interpreter.md

+7-5
Original file line numberDiff line numberDiff line change
@@ -127,11 +127,13 @@ the same. Cache entries are reserved by the compiler and initialized with zeros
127127
Although they are represented by code units, cache entries do not conform to the
128128
`opcode` / `oparg` format.
129129

130-
If an instruction has an inline cache, the layout of its cache is described by
131-
a `struct` definition in [`pycore_code.h`](../Include/internal/pycore_code.h).
132-
This allows us to access the cache by casting `next_instr` to a pointer to this `struct`.
133-
The size of such a `struct` must be independent of the machine architecture, word size
134-
and alignment requirements. For a 32-bit field, the `struct` should use `_Py_CODEUNIT field[2]`.
130+
If an instruction has an inline cache, the layout of its cache is described in
131+
the instruction's definition in [`Python/bytecodes.c`](../Python/bytecodes.c).
132+
The structs defined in [`pycore_code.h`](../Include/internal/pycore_code.h)
133+
allow us to access the cache by casting `next_instr` to a pointer to the relevant
134+
`struct`. The size of such a `struct` must be independent of the machine
135+
architecture, word size and alignment requirements. For a 32-bit field, the
136+
`struct` should use `_Py_CODEUNIT field[2]`.
135137

136138
The instruction implementation is responsible for advancing `next_instr` past the inline cache.
137139
For example, if an instruction's inline cache is four bytes (that is, two code units) in size,

0 commit comments

Comments
 (0)