From e597f51fad4e8f3c3fd3bacbb45ea08f7d8b00dc Mon Sep 17 00:00:00 2001 From: Chenyu Yang Date: Wed, 3 Jul 2024 00:27:17 +0800 Subject: [PATCH 1/3] Add support for detecting Intel P-Cores --- include/cpuinfo.h | 13 +++++++++++++ src/x86/uarch.c | 26 ++++++++++++++++++++++++++ tools/cpu-info.c | 13 +++++++++++++ 3 files changed, 52 insertions(+) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 2d74b62f..4e28b336 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -353,6 +353,19 @@ enum cpuinfo_uarch { cpuinfo_uarch_palm_cove = 0x0010020B, /** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */ cpuinfo_uarch_sunny_cove = 0x0010020C, + /** Intel Cypress Cove microarchitecture (14 nm, Rocket Lake) */ + cpuinfo_uarch_cypress_cove = 0x0010020E, + /** Intel Golden Cove microarchitecture (Intel 7, Alder Lake P-Cores) */ + cpuinfo_uarch_golden_cove = 0x0010020F, + /** Intel Gracemont Cove microarchitecture (Intel 7, Alder/Raptor Lake E-Cores) */ + cpuinfo_uarch_gracemont_cove = 0x00100210, + /** Intel Raptor Cove microarchitecture (Intel 7, Raptor Lake P-Cores) */ + cpuinfo_uarch_raptor_cove = 0x00100211, + /** Intel Redwood Cove microarchitecture (Intel 4, Meteor Lake P-Cores) */ + cpuinfo_uarch_redwood_cove = 0x00100212, + /** Intel Crestmont Cove microarchitecture (Intel 4, Meteor Lake E-Cores/LP-E-Cores) */ + cpuinfo_uarch_crestmont_cove = 0x00100213, + /** Pentium 4 with Willamette, Northwood, or Foster cores. */ cpuinfo_uarch_willamette = 0x00100300, diff --git a/src/x86/uarch.c b/src/x86/uarch.c index b291ebcf..199f25f8 100644 --- a/src/x86/uarch.c +++ b/src/x86/uarch.c @@ -2,6 +2,12 @@ #include #include +#include + +CPUINFO_INTERNAL bool cpuinfo_x86_detect_pcores(){ + if (((cpuid(0x1A).eax >> 24) & 0xFFF) == 0x40) return true; + return false; +} enum cpuinfo_uarch cpuinfo_x86_decode_uarch( enum cpuinfo_vendor vendor, @@ -167,6 +173,26 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x7D: // Ice Lake-Y case 0x7E: // Ice Lake-U return cpuinfo_uarch_sunny_cove; + case 0xA7: // Rocket Lake + return cpuinfo_uarch_cypress_cove; + case 0x9A: // Alder Lake + if (cpuinfo_x86_detect_pcores()){ + return cpuinfo_uarch_golden_cove; + } else { // E Core + return cpuinfo_uarch_gracemont_cove; + } + case 0xB7: // Raptor Lake + if (cpuinfo_x86_detect_pcores()){ + return cpuinfo_uarch_raptor_cove; + } else { // E Core + return cpuinfo_uarch_gracemont_cove; + } + case 0xAA: // Meteor Lake + if (cpuinfo_x86_detect_pcores()){ + return cpuinfo_uarch_redwood_cove; + } else { // E/LP-E Core + return cpuinfo_uarch_crestmont_cove; + } /* Low-power cores */ case 0x1C: // Diamondville, diff --git a/tools/cpu-info.c b/tools/cpu-info.c index a4ace204..a89e3998 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -80,6 +80,19 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Palm Cove"; case cpuinfo_uarch_sunny_cove: return "Sunny Cove"; + case cpuinfo_uarch_cypress_cove: + return "Cypress Cove"; + case cpuinfo_uarch_golden_cove: + return "Golden Cove"; + case cpuinfo_uarch_gracemont_cove: + return "Gracemont Cove"; + case cpuinfo_uarch_raptor_cove: + return "Raptor Cove"; + case cpuinfo_uarch_redwood_cove: + return "Redwood Cove"; + case cpuinfo_uarch_crestmont_cove: + return "Crestmont Cove"; + case cpuinfo_uarch_willamette: return "Willamette"; case cpuinfo_uarch_prescott: From a3d5dc100307ef952c2d11253bf80e64d6420750 Mon Sep 17 00:00:00 2001 From: Chenyu Yang Date: Thu, 4 Jul 2024 18:08:21 +0800 Subject: [PATCH 2/3] Removed 'cove' from the end of Gracemont and Crestmont. --- include/cpuinfo.h | 8 ++++---- src/x86/uarch.c | 6 +++--- tools/cpu-info.c | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 4e28b336..fa96b380 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -357,14 +357,14 @@ enum cpuinfo_uarch { cpuinfo_uarch_cypress_cove = 0x0010020E, /** Intel Golden Cove microarchitecture (Intel 7, Alder Lake P-Cores) */ cpuinfo_uarch_golden_cove = 0x0010020F, - /** Intel Gracemont Cove microarchitecture (Intel 7, Alder/Raptor Lake E-Cores) */ - cpuinfo_uarch_gracemont_cove = 0x00100210, + /** Intel Gracemont microarchitecture (Intel 7, Alder/Raptor Lake E-Cores) */ + cpuinfo_uarch_gracemont = 0x00100210, /** Intel Raptor Cove microarchitecture (Intel 7, Raptor Lake P-Cores) */ cpuinfo_uarch_raptor_cove = 0x00100211, /** Intel Redwood Cove microarchitecture (Intel 4, Meteor Lake P-Cores) */ cpuinfo_uarch_redwood_cove = 0x00100212, - /** Intel Crestmont Cove microarchitecture (Intel 4, Meteor Lake E-Cores/LP-E-Cores) */ - cpuinfo_uarch_crestmont_cove = 0x00100213, + /** Intel Crestmont microarchitecture (Intel 4, Meteor Lake E-Cores/LP-E-Cores) */ + cpuinfo_uarch_crestmont = 0x00100213, /** Pentium 4 with Willamette, Northwood, or Foster cores. */ diff --git a/src/x86/uarch.c b/src/x86/uarch.c index 199f25f8..a513accd 100644 --- a/src/x86/uarch.c +++ b/src/x86/uarch.c @@ -179,19 +179,19 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( if (cpuinfo_x86_detect_pcores()){ return cpuinfo_uarch_golden_cove; } else { // E Core - return cpuinfo_uarch_gracemont_cove; + return cpuinfo_uarch_gracemont; } case 0xB7: // Raptor Lake if (cpuinfo_x86_detect_pcores()){ return cpuinfo_uarch_raptor_cove; } else { // E Core - return cpuinfo_uarch_gracemont_cove; + return cpuinfo_uarch_gracemont; } case 0xAA: // Meteor Lake if (cpuinfo_x86_detect_pcores()){ return cpuinfo_uarch_redwood_cove; } else { // E/LP-E Core - return cpuinfo_uarch_crestmont_cove; + return cpuinfo_uarch_crestmont; } /* Low-power cores */ diff --git a/tools/cpu-info.c b/tools/cpu-info.c index a89e3998..945b8733 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -84,14 +84,14 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Cypress Cove"; case cpuinfo_uarch_golden_cove: return "Golden Cove"; - case cpuinfo_uarch_gracemont_cove: - return "Gracemont Cove"; + case cpuinfo_uarch_gracemont: + return "Gracemont"; case cpuinfo_uarch_raptor_cove: return "Raptor Cove"; case cpuinfo_uarch_redwood_cove: return "Redwood Cove"; - case cpuinfo_uarch_crestmont_cove: - return "Crestmont Cove"; + case cpuinfo_uarch_crestmont: + return "Crestmont"; case cpuinfo_uarch_willamette: return "Willamette"; From 33725abcb6e8ef998a53090e9455eb9544d91c7c Mon Sep 17 00:00:00 2001 From: Chenyu Yang Date: Wed, 24 Jul 2024 18:37:36 +0800 Subject: [PATCH 3/3] Added new model ids for Rocket/Alder/Meteor Lake --- src/x86/uarch.c | 45 +++++++++++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/src/x86/uarch.c b/src/x86/uarch.c index a513accd..6ed53ffb 100644 --- a/src/x86/uarch.c +++ b/src/x86/uarch.c @@ -4,8 +4,8 @@ #include #include -CPUINFO_INTERNAL bool cpuinfo_x86_detect_pcores(){ - if (((cpuid(0x1A).eax >> 24) & 0xFFF) == 0x40) return true; +CPUINFO_INTERNAL bool cpuinfo_x86_detect_hybrid_ecore(){ + if (((cpuid(0x1A).eax >> 24) & 0xFFF) == 0x20) return true; return false; } @@ -174,24 +174,45 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x7E: // Ice Lake-U return cpuinfo_uarch_sunny_cove; case 0xA7: // Rocket Lake + case 0xA8: // Rocket Lake return cpuinfo_uarch_cypress_cove; - case 0x9A: // Alder Lake - if (cpuinfo_x86_detect_pcores()){ - return cpuinfo_uarch_golden_cove; - } else { // E Core + case 0x97: // Alder Lake + // (S-processor 8+8) + // (HX SBGA - processor 8+8) + // (S-processor 6+0) + case 0x9A: // Alder Lake + // (P-processor 6+8) + // (H-processor 6+8) + // (U15-processor 2+8) + // (U9-processor 2+8) + if (cpuinfo_x86_detect_hybrid_ecore()){ return cpuinfo_uarch_gracemont; + } else { + return cpuinfo_uarch_golden_cove; } case 0xB7: // Raptor Lake - if (cpuinfo_x86_detect_pcores()){ - return cpuinfo_uarch_raptor_cove; - } else { // E Core + // (S/S Refresh 8P+16E ) + // (HX/HX Refresh 8P+16E) + // (E 8P+0E) + case 0xBF: // Raptor Lake + // (S/S Refresh 8P+8E) + // (S/S Refresh 6P+0E) + // (HX 8P+8E) + case 0xBA: // Raptor Lake + // (H 6P+8E) + // (P 6P+8E) + // (PX 6E+8P) + // (U/U Refresh 2E+8P) + if (cpuinfo_x86_detect_hybrid_ecore()){ return cpuinfo_uarch_gracemont; + } else { + return cpuinfo_uarch_raptor_cove; } case 0xAA: // Meteor Lake - if (cpuinfo_x86_detect_pcores()){ - return cpuinfo_uarch_redwood_cove; - } else { // E/LP-E Core + if (cpuinfo_x86_detect_hybrid_ecore()){ return cpuinfo_uarch_crestmont; + } else { + return cpuinfo_uarch_redwood_cove; } /* Low-power cores */