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bramathonjselig-rigetti
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Cleaned up formatting for quil_input_test
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cirq-rigetti/cirq_rigetti/quil_input_test.py

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Original file line numberDiff line numberDiff line change
@@ -12,9 +12,11 @@
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# See the License for the specific language governing permissions and
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# limitations under the License.
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from inspect import signature
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import numpy as np
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import pytest
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from inspect import signature
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from pyquil.quil import Program
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from pyquil.simulation import matrices
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from pyquil.simulation.tools import program_unitary
@@ -47,9 +49,6 @@
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def test_gate_conversion():
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"""Check that the gates all convert with matching unitaries."""
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for quil_gate, cirq_gate in SUPPORTED_GATES.items():
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# pyquil has an error in the RYY defintion
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if quil_gate == "RYY":
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continue
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if quil_gate in PARAMETRIC_TRANSFORMERS:
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pyquil_def = getattr(matrices, quil_gate)
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sig = signature(pyquil_def)
@@ -93,6 +92,7 @@ def test_gate_conversion():
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XY(pi/2) 1 2
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RZZ(pi/2) 0 1
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RXX(pi/2) 1 2
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RYY(pi/2) 0 2
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FSIM(pi/4, pi/8) 1 2
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PHASEDFSIM(pi/4, -pi/6, pi/2, pi/3, pi/8) 0 1
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CCNOT 0 1 2
@@ -135,6 +135,7 @@ def test_circuit_from_quil():
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ISwapPowGate(exponent=1 / 2, global_shift=0.0)(q1, q2),
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ZZPowGate(exponent=1 / 2, global_shift=-0.5)(q0, q1),
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XXPowGate(exponent=1 / 2, global_shift=-0.5)(q1, q2),
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YYPowGate(exponent=1 / 2, global_shift=-0.5)(q0, q2),
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FSimGate(theta=-np.pi / 8, phi=-np.pi / 8)(q1, q2),
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PhasedFSimGate(
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theta=-np.pi / 8, zeta=-np.pi / 6, chi=np.pi / 2, gamma=np.pi / 3, phi=-np.pi / 8
@@ -149,8 +150,6 @@ def test_circuit_from_quil():
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# build the same Circuit, using Quil
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quil_circuit = circuit_from_quil(Program(QUIL_PROGRAM))
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# test Circuit equivalence
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print(cirq_circuit)
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print(quil_circuit)
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assert cirq_circuit == quil_circuit
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pyquil_circuit = Program(QUIL_PROGRAM)

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