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Remove leftover dummy terms from the Cirq sources (#6358)
Follow up to #6356. Replace non-inclusive terminology.
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5 files changed

+12
-12
lines changed

5 files changed

+12
-12
lines changed

cirq-aqt/cirq_aqt/aqt_sampler_test.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ def test_aqt_sampler_ms():
204204
_, qubits = get_aqt_device(num_qubits)
205205
sampler = AQTSamplerLocalSimulator()
206206
circuit = cirq.Circuit(cirq.Z.on_each(*qubits), cirq.Z.on_each(*qubits))
207-
for _dummy in range(9):
207+
for _ in range(9):
208208
circuit.append(cirq.XX(qubits[0], qubits[1]) ** 0.5)
209209
circuit.append(cirq.Z(qubits[0]) ** 0.5)
210210
results = sampler.run(circuit, repetitions=repetitions)

cirq-ft/cirq_ft/algos/mean_estimation/complex_phase_oracle_test.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727

2828

2929
@frozen
30-
class DummySelect(cirq_ft.SelectOracle):
30+
class ExampleSelect(cirq_ft.SelectOracle):
3131
bitsize: int
3232
control_val: Optional[int] = None
3333

@@ -50,7 +50,7 @@ def decompose_from_registers(self, context, selection, target):
5050
@pytest.mark.parametrize('bitsize', [2, 3, 4, 5])
5151
@pytest.mark.parametrize('arctan_bitsize', [5, 6, 7])
5252
def test_phase_oracle(bitsize: int, arctan_bitsize: int):
53-
phase_oracle = ComplexPhaseOracle(DummySelect(bitsize), arctan_bitsize)
53+
phase_oracle = ComplexPhaseOracle(ExampleSelect(bitsize), arctan_bitsize)
5454
g = cq_testing.GateHelper(phase_oracle)
5555

5656
# Prepare uniform superposition state on selection register and apply phase oracle.
@@ -78,6 +78,6 @@ def test_phase_oracle(bitsize: int, arctan_bitsize: int):
7878

7979
def test_phase_oracle_consistent_protocols():
8080
bitsize, arctan_bitsize = 3, 5
81-
gate = ComplexPhaseOracle(DummySelect(bitsize, 1), arctan_bitsize)
81+
gate = ComplexPhaseOracle(ExampleSelect(bitsize, 1), arctan_bitsize)
8282
expected_symbols = ('@',) + ('ROTy',) * bitsize
8383
assert cirq.circuit_diagram_info(gate).wire_symbols == expected_symbols

cirq-ft/cirq_ft/infra/jupyter_tools_test.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -39,10 +39,10 @@ def test_svg_circuit():
3939
def test_display_gate_and_compilation(monkeypatch):
4040
call_args = []
4141

42-
def _dummy_display(stuff):
42+
def _mock_display(stuff):
4343
call_args.append(stuff)
4444

45-
monkeypatch.setattr(IPython.display, "display", _dummy_display)
45+
monkeypatch.setattr(IPython.display, "display", _mock_display)
4646
g = cq_testing.GateHelper(cirq_ft.And(cv=(1, 1, 1)))
4747
display_gate_and_compilation(g)
4848

cirq-google/cirq_google/calibration/engine_simulator_test.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
SQRT_ISWAP_INV_GATE = cirq.FSimGate(np.pi / 4, 0.0)
2828

2929

30-
class DummyPhasedFSimCalibrationRequest(PhasedFSimCalibrationRequest):
30+
class ExamplePhasedFSimCalibrationRequest(PhasedFSimCalibrationRequest):
3131
def to_calibration_layer(self) -> cirq_google.CalibrationLayer:
3232
return NotImplemented
3333

@@ -39,7 +39,7 @@ def parse_result(
3939

4040
def test_test_calibration_request():
4141
a, b = cirq.LineQubit.range(2)
42-
request = DummyPhasedFSimCalibrationRequest(
42+
request = ExamplePhasedFSimCalibrationRequest(
4343
gate=cirq.FSimGate(np.pi / 4, 0.5),
4444
pairs=((a, b),),
4545
options=ALL_ANGLES_FLOQUET_PHASED_FSIM_CHARACTERIZATION,
@@ -108,7 +108,7 @@ def test_floquet_get_calibrations_when_invalid_request_fails():
108108
with pytest.raises(ValueError):
109109
engine_simulator.get_calibrations(
110110
[
111-
DummyPhasedFSimCalibrationRequest(
111+
ExamplePhasedFSimCalibrationRequest(
112112
gate=cirq.FSimGate(np.pi / 4, 0.5),
113113
pairs=((a, b),),
114114
options=ALL_ANGLES_FLOQUET_PHASED_FSIM_CHARACTERIZATION,

cirq-google/cirq_google/workflow/processor_record_test.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -20,13 +20,13 @@
2020
import cirq_google as cg
2121

2222

23-
class _DummyProcessorRecord(cg.ProcessorRecord):
23+
class _ExampleProcessorRecord(cg.ProcessorRecord):
2424
def get_processor(self) -> 'cg.engine.AbstractProcessor':
25-
return cg.engine.SimulatedLocalProcessor(processor_id='dummy')
25+
return cg.engine.SimulatedLocalProcessor(processor_id='example')
2626

2727

2828
def test_abstract_processor_record():
29-
proc_rec = _DummyProcessorRecord()
29+
proc_rec = _ExampleProcessorRecord()
3030
assert isinstance(proc_rec.get_processor(), cg.engine.AbstractProcessor)
3131
assert isinstance(proc_rec.get_sampler(), cirq.Sampler)
3232
assert isinstance(proc_rec.get_device(), cirq.Device)

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