Differentiate unitary/channel/stabilizer gates/ops/circuits at the type level

[daxfohl]

Is your design idea/issue related to a use case or problem? Please describe.

Semi-related to #1740, #4582

Describe your design idea/issue

Currently simulators fail at runtime when they encounter a gate they can't handle. It seems like there should be a way to prevent this at the type level. Simulators should be able to specify what types of gates they can handle, and gates should be able to specify what type they are. Additionally simulators should perhaps externalize the prng, such that e.g. state vector simulator can do .simulate(unitary_circuit) and .simulate(channel_circuit, prng) but not .simulate(channel_circuit), so that it's explicit when non-determinism is involved.

I don't have a specific design in mind, but wondering whether it's worth investigating. Concerns are, would this lead to a quadratic or worse explosion of op types and things that operate on them (I think this is avoidable, but not sure), and also whether the ROI would be high enough (it's probably a pretty big project and would likely require breaking changes; on the flip side this explicitness could make cirq easier to use in other ways too).

[daxfohl]

One challenge is some gates have different characteristics depending on parameters. i.e. stabilizer gates may only be stabilizers if they have integer exponents.

[daxfohl]

Closing due to too big, too many unknowns, prefer "pythonic" protocol based.