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Commit 2aa6dd0

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Mike Turquette
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Merge tag 'socfpga-clk-fix-for-3.15' of git://git.rocketboards.org/linux-socfpga-next into clk-fixes-socfpga
clk: socfpga: clock fix for v3.15 Currently on 3.15-rc1, the SOCFPGA platform is unable to boot. This patch fixes the issue and allows the platform to boot.
2 parents dd23c2c + a30d27e commit 2aa6dd0

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2 files changed

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-20
lines changed

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-20
lines changed

drivers/clk/socfpga/clk-pll.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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@@ -43,6 +44,8 @@
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#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
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void __iomem *clk_mgr_base_addr;
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
@@ -87,6 +90,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct device_node *clkmgr_np;
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int rc;
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int i = 0;
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@@ -96,6 +100,9 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
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if (WARN_ON(!pll_clk))
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return NULL;
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clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
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clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
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BUG_ON(!clk_mgr_base_addr);
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pll_clk->hw.reg = clk_mgr_base_addr + reg;
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of_property_read_string(node, "clock-output-names", &clk_name);

drivers/clk/socfpga/clk.c

Lines changed: 3 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -17,28 +17,11 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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void __iomem *clk_mgr_base_addr;
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static const struct of_device_id socfpga_child_clocks[] __initconst = {
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{ .compatible = "altr,socfpga-pll-clock", socfpga_pll_init, },
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{ .compatible = "altr,socfpga-perip-clk", socfpga_periph_init, },
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{ .compatible = "altr,socfpga-gate-clk", socfpga_gate_init, },
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{},
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};
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static void __init socfpga_clkmgr_init(struct device_node *node)
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{
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clk_mgr_base_addr = of_iomap(node, 0);
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of_clk_init(socfpga_child_clocks);
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}
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CLK_OF_DECLARE(socfpga_mgr, "altr,clk-mgr", socfpga_clkmgr_init);
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CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
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CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
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CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);
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