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Kuogee Hsiehrobclark
Kuogee Hsieh
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drm/msm/dp: do not end dp link training until video is ready
Initialize both pre-emphasis and voltage swing level to 0 before start link training and do not end link training until video is ready to reduce the period between end of link training and video start to meet Link Layer CTS requirement. Some dongle main link symbol may become unlocked again if host did not end link training soon enough after completion of link training 2. Host have to re train main link if loss of symbol locked detected before end link training so that the coming video stream can be transmitted to sink properly. This fixes Link Layer CTS cases 4.3.2.1, 4.3.2.2, 4.3.2.3 and 4.3.2.4. Changes in v3: -- merge retrain link if loss of symbol locked happen into this patch -- replace dp_ctrl_loss_symbol_lock() with dp_ctrl_channel_eq_ok() Signed-off-by: Kuogee Hsieh <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Clark <[email protected]>
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drivers/gpu/drm/msm/dp/dp_ctrl.c

Lines changed: 41 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1483,6 +1483,9 @@ static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
14831483

14841484
dp_ctrl_push_idle(&ctrl->dp_ctrl);
14851485

1486+
ctrl->link->phy_params.p_level = 0;
1487+
ctrl->link->phy_params.v_level = 0;
1488+
14861489
ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
14871490

14881491
ret = dp_ctrl_setup_main_link(ctrl, &training_step);
@@ -1635,6 +1638,16 @@ static bool dp_ctrl_clock_recovery_any_ok(
16351638
return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
16361639
}
16371640

1641+
static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1642+
{
1643+
u8 link_status[DP_LINK_STATUS_SIZE];
1644+
int num_lanes = ctrl->link->link_params.num_lanes;
1645+
1646+
dp_ctrl_read_link_status(ctrl, link_status);
1647+
1648+
return drm_dp_channel_eq_ok(link_status, num_lanes);
1649+
}
1650+
16381651
int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
16391652
{
16401653
int rc = 0;
@@ -1669,6 +1682,9 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
16691682
ctrl->link->link_params.rate,
16701683
ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
16711684

1685+
ctrl->link->phy_params.p_level = 0;
1686+
ctrl->link->phy_params.v_level = 0;
1687+
16721688
rc = dp_ctrl_enable_mainlink_clocks(ctrl);
16731689
if (rc)
16741690
return rc;
@@ -1734,27 +1750,35 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
17341750
if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
17351751
return rc;
17361752

1737-
/* stop txing train pattern */
1738-
dp_ctrl_clear_training_pattern(ctrl);
1753+
if (rc == 0) { /* link train successfully */
1754+
/*
1755+
* do not stop train pattern here
1756+
* stop link training at on_stream
1757+
* to pass compliance test
1758+
*/
1759+
} else {
1760+
/*
1761+
* link training failed
1762+
* end txing train pattern here
1763+
*/
1764+
dp_ctrl_clear_training_pattern(ctrl);
17391765

1740-
/*
1741-
* keep transmitting idle pattern until video ready
1742-
* to avoid main link from loss of sync
1743-
*/
1744-
if (rc == 0) /* link train successfully */
1745-
dp_ctrl_push_idle(dp_ctrl);
1746-
else {
1747-
/* link training failed */
17481766
dp_ctrl_deinitialize_mainlink(ctrl);
17491767
rc = -ECONNRESET;
17501768
}
17511769

17521770
return rc;
17531771
}
17541772

1773+
static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1774+
{
1775+
int training_step = DP_TRAINING_NONE;
1776+
1777+
return dp_ctrl_setup_main_link(ctrl, &training_step);
1778+
}
1779+
17551780
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
17561781
{
1757-
u32 rate = 0;
17581782
int ret = 0;
17591783
bool mainlink_ready = false;
17601784
struct dp_ctrl_private *ctrl;
@@ -1764,10 +1788,6 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
17641788

17651789
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
17661790

1767-
rate = ctrl->panel->link_info.rate;
1768-
1769-
ctrl->link->link_params.rate = rate;
1770-
ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes;
17711791
ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
17721792

17731793
DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
@@ -1782,6 +1802,12 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
17821802
}
17831803
}
17841804

1805+
if (!dp_ctrl_channel_eq_ok(ctrl))
1806+
dp_ctrl_link_retrain(ctrl);
1807+
1808+
/* stop txing train pattern to end link training */
1809+
dp_ctrl_clear_training_pattern(ctrl);
1810+
17851811
ret = dp_ctrl_enable_stream_clocks(ctrl);
17861812
if (ret) {
17871813
DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);

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