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Sylvain Lemieuxlinusw
Sylvain Lemieux
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gpio: lpc32xx: disable broken to_irq support
The "to_irq" functionality is broken inside this driver since commit 76ba59f ("genirq: Add irq_domain-aware core IRQ handler"). The addition of the new lpc32xx irqchip driver in 4.7, fixed the lpc32xx platform interrupt issue. When switching to the new lpc32xx irqchip driver, a warning appear in the lpc32xx gpio driver: warning: "NR_IRQS" redefined. To remove this warning (temporary solution), this patch disables the broken "to_irq" mapping functionality support. Signed-off-by: Sylvain Lemieux <[email protected]> Acked-by: Vladimir Zapolskiy <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
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drivers/gpio/gpio-lpc32xx.c

Lines changed: 1 addition & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@
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3030
#include <mach/hardware.h>
3131
#include <mach/platform.h>
32-
#include <mach/irqs.h>
3332

3433
#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
3534
#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
@@ -371,61 +370,16 @@ static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
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372371
static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
373372
{
374-
return IRQ_LPC32XX_P0_P1_IRQ;
373+
return -ENXIO;
375374
}
376375

377-
static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
378-
IRQ_LPC32XX_GPIO_00,
379-
IRQ_LPC32XX_GPIO_01,
380-
IRQ_LPC32XX_GPIO_02,
381-
IRQ_LPC32XX_GPIO_03,
382-
IRQ_LPC32XX_GPIO_04,
383-
IRQ_LPC32XX_GPIO_05,
384-
};
385-
386376
static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
387377
{
388-
if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
389-
return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
390378
return -ENXIO;
391379
}
392380

393-
static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
394-
IRQ_LPC32XX_GPI_00,
395-
IRQ_LPC32XX_GPI_01,
396-
IRQ_LPC32XX_GPI_02,
397-
IRQ_LPC32XX_GPI_03,
398-
IRQ_LPC32XX_GPI_04,
399-
IRQ_LPC32XX_GPI_05,
400-
IRQ_LPC32XX_GPI_06,
401-
IRQ_LPC32XX_GPI_07,
402-
IRQ_LPC32XX_GPI_08,
403-
IRQ_LPC32XX_GPI_09,
404-
-ENXIO, /* 10 */
405-
-ENXIO, /* 11 */
406-
-ENXIO, /* 12 */
407-
-ENXIO, /* 13 */
408-
-ENXIO, /* 14 */
409-
-ENXIO, /* 15 */
410-
-ENXIO, /* 16 */
411-
-ENXIO, /* 17 */
412-
-ENXIO, /* 18 */
413-
IRQ_LPC32XX_GPI_19,
414-
-ENXIO, /* 20 */
415-
-ENXIO, /* 21 */
416-
-ENXIO, /* 22 */
417-
-ENXIO, /* 23 */
418-
-ENXIO, /* 24 */
419-
-ENXIO, /* 25 */
420-
-ENXIO, /* 26 */
421-
-ENXIO, /* 27 */
422-
IRQ_LPC32XX_GPI_28,
423-
};
424-
425381
static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
426382
{
427-
if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
428-
return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
429383
return -ENXIO;
430384
}
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