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andy-shevgregkh
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pinctrl: cy8c95x0: Rename PWMSEL to SELPWM
[ Upstream commit 0a7404f ] There are two registers in the hardware, one, "Select PWM", is per-port configuration enabling PWM function instead of GPIO. The other one is "PWM Select" is per-PWM selector to configure PWM itself. Original code uses abbreviation of the latter to describe the former. Rename it to follow the datasheet. Fixes: e6cbbe4 ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
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drivers/pinctrl/pinctrl-cy8c95x0.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
#define CY8C95X0_PORTSEL 0x18
4343
/* Port settings, write PORTSEL first */
4444
#define CY8C95X0_INTMASK 0x19
45-
#define CY8C95X0_PWMSEL 0x1A
45+
#define CY8C95X0_SELPWM 0x1A
4646
#define CY8C95X0_INVERT 0x1B
4747
#define CY8C95X0_DIRECTION 0x1C
4848
/* Drive mode register change state on writing '1' */
@@ -371,8 +371,8 @@ static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
371371
case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
372372
case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
373373
case CY8C95X0_INTMASK:
374+
case CY8C95X0_SELPWM:
374375
case CY8C95X0_INVERT:
375-
case CY8C95X0_PWMSEL:
376376
case CY8C95X0_DIRECTION:
377377
case CY8C95X0_DRV_PU:
378378
case CY8C95X0_DRV_PD:
@@ -401,7 +401,7 @@ static bool cy8c95x0_muxed_register(unsigned int reg)
401401
{
402402
switch (reg) {
403403
case CY8C95X0_INTMASK:
404-
case CY8C95X0_PWMSEL:
404+
case CY8C95X0_SELPWM:
405405
case CY8C95X0_INVERT:
406406
case CY8C95X0_DIRECTION:
407407
case CY8C95X0_DRV_PU:
@@ -807,7 +807,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
807807
reg = CY8C95X0_DIRECTION;
808808
break;
809809
case PIN_CONFIG_MODE_PWM:
810-
reg = CY8C95X0_PWMSEL;
810+
reg = CY8C95X0_SELPWM;
811811
break;
812812
case PIN_CONFIG_OUTPUT:
813813
reg = CY8C95X0_OUTPUT;
@@ -889,7 +889,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
889889
reg = CY8C95X0_DRV_PP_FAST;
890890
break;
891891
case PIN_CONFIG_MODE_PWM:
892-
reg = CY8C95X0_PWMSEL;
892+
reg = CY8C95X0_SELPWM;
893893
break;
894894
case PIN_CONFIG_OUTPUT_ENABLE:
895895
ret = cy8c95x0_pinmux_direction(chip, off, !arg);
@@ -1179,7 +1179,7 @@ static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *
11791179
bitmap_zero(mask, MAX_LINE);
11801180
__set_bit(pin, mask);
11811181

1182-
if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1182+
if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) {
11831183
seq_puts(s, "not available");
11841184
return;
11851185
}
@@ -1224,7 +1224,7 @@ static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bo
12241224
u8 port = cypress_get_port(chip, off);
12251225
u8 bit = cypress_get_pin_mask(chip, off);
12261226

1227-
return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);
1227+
return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0);
12281228
}
12291229

12301230
static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,

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