|
42 | 42 | #define CY8C95X0_PORTSEL 0x18
|
43 | 43 | /* Port settings, write PORTSEL first */
|
44 | 44 | #define CY8C95X0_INTMASK 0x19
|
45 |
| -#define CY8C95X0_PWMSEL 0x1A |
| 45 | +#define CY8C95X0_SELPWM 0x1A |
46 | 46 | #define CY8C95X0_INVERT 0x1B
|
47 | 47 | #define CY8C95X0_DIRECTION 0x1C
|
48 | 48 | /* Drive mode register change state on writing '1' */
|
@@ -371,8 +371,8 @@ static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
|
371 | 371 | case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
|
372 | 372 | case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
|
373 | 373 | case CY8C95X0_INTMASK:
|
| 374 | + case CY8C95X0_SELPWM: |
374 | 375 | case CY8C95X0_INVERT:
|
375 |
| - case CY8C95X0_PWMSEL: |
376 | 376 | case CY8C95X0_DIRECTION:
|
377 | 377 | case CY8C95X0_DRV_PU:
|
378 | 378 | case CY8C95X0_DRV_PD:
|
@@ -401,7 +401,7 @@ static bool cy8c95x0_muxed_register(unsigned int reg)
|
401 | 401 | {
|
402 | 402 | switch (reg) {
|
403 | 403 | case CY8C95X0_INTMASK:
|
404 |
| - case CY8C95X0_PWMSEL: |
| 404 | + case CY8C95X0_SELPWM: |
405 | 405 | case CY8C95X0_INVERT:
|
406 | 406 | case CY8C95X0_DIRECTION:
|
407 | 407 | case CY8C95X0_DRV_PU:
|
@@ -807,7 +807,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
|
807 | 807 | reg = CY8C95X0_DIRECTION;
|
808 | 808 | break;
|
809 | 809 | case PIN_CONFIG_MODE_PWM:
|
810 |
| - reg = CY8C95X0_PWMSEL; |
| 810 | + reg = CY8C95X0_SELPWM; |
811 | 811 | break;
|
812 | 812 | case PIN_CONFIG_OUTPUT:
|
813 | 813 | reg = CY8C95X0_OUTPUT;
|
@@ -889,7 +889,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
|
889 | 889 | reg = CY8C95X0_DRV_PP_FAST;
|
890 | 890 | break;
|
891 | 891 | case PIN_CONFIG_MODE_PWM:
|
892 |
| - reg = CY8C95X0_PWMSEL; |
| 892 | + reg = CY8C95X0_SELPWM; |
893 | 893 | break;
|
894 | 894 | case PIN_CONFIG_OUTPUT_ENABLE:
|
895 | 895 | ret = cy8c95x0_pinmux_direction(chip, off, !arg);
|
@@ -1179,7 +1179,7 @@ static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *
|
1179 | 1179 | bitmap_zero(mask, MAX_LINE);
|
1180 | 1180 | __set_bit(pin, mask);
|
1181 | 1181 |
|
1182 |
| - if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) { |
| 1182 | + if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) { |
1183 | 1183 | seq_puts(s, "not available");
|
1184 | 1184 | return;
|
1185 | 1185 | }
|
@@ -1224,7 +1224,7 @@ static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bo
|
1224 | 1224 | u8 port = cypress_get_port(chip, off);
|
1225 | 1225 | u8 bit = cypress_get_pin_mask(chip, off);
|
1226 | 1226 |
|
1227 |
| - return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0); |
| 1227 | + return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0); |
1228 | 1228 | }
|
1229 | 1229 |
|
1230 | 1230 | static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
|
|
0 commit comments