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gianfar: Use Single-Queue polling for "fsl,etsec2"
For the "fsl,etsec2" compatible models the driver currently supports 8 Tx and Rx DMA rings (aka HW queues). However, there are only 2 pairs of Rx/Tx interrupt lines, as these controllers are integrated in low power SoCs with 2 CPUs at most. As a result, there are at most 2 NAPI instances that have to service multiple Tx and Rx queues for these devices. This complicates the NAPI polling routine having to iterate over the mutiple Rx/Tx queues hooked to the same interrupt lines. And there's also an overhead at HW level, as the controller needs to service all the 8 Tx rings in a round robin manner. The combined overhead shows up for multi parallel Tx flows transmitted by the kernel stack, when the driver usually starts returning NETDEV_TX_BUSY leading to NETDEV WATCHDOG Tx timeout triggering if the Tx path is congested for too long. As an alternative, this patch makes the driver support only one Tx/Rx DMA ring per NAPI instance (per interrupt group or pair of Tx/Rx interrupt lines) by default. The simplified single queue polling routine (gfar_poll_sq) will be the default napi poll routine for the etsec2 devices too. Some adjustments needed to be made to link the Tx/Rx HW queues with each NAPI instance (2 in this case). The gfar_poll_sq() is already successfully used by older SQ_SG_MODE (single interrupt group) controllers. This patch fixes Tx timeout triggering under heavy Tx traffic load (i.e. iperf -c -P 8) for the "fsl,etsec2" (currently the only MQ_MG_MODE devices). There's also a significant memory footprint reduction by supporting 2 Rx/Tx DMA rings (at most), instead of 8, for these devices. Signed-off-by: Claudiu Manoil <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/ethernet/freescale/gianfar.c

Lines changed: 48 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -363,7 +363,10 @@ static void gfar_mac_rx_config(struct gfar_private *priv)
363363
if (priv->rx_filer_enable) {
364364
rctrl |= RCTRL_FILREN;
365365
/* Program the RIR0 reg with the required distribution */
366-
gfar_write(&regs->rir0, DEFAULT_RIR0);
366+
if (priv->poll_mode == GFAR_SQ_POLLING)
367+
gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
368+
else /* GFAR_MQ_POLLING */
369+
gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
367370
}
368371

369372
/* Restore PROMISC mode */
@@ -636,7 +639,6 @@ static int gfar_parse_group(struct device_node *np,
636639
struct gfar_private *priv, const char *model)
637640
{
638641
struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
639-
u32 *queue_mask;
640642
int i;
641643

642644
for (i = 0; i < GFAR_NUM_IRQS; i++) {
@@ -665,12 +667,20 @@ static int gfar_parse_group(struct device_node *np,
665667
grp->priv = priv;
666668
spin_lock_init(&grp->grplock);
667669
if (priv->mode == MQ_MG_MODE) {
668-
queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
669-
grp->rx_bit_map = queue_mask ?
670-
*queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
671-
queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
672-
grp->tx_bit_map = queue_mask ?
673-
*queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
670+
u32 *rxq_mask, *txq_mask;
671+
rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
672+
txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
673+
674+
if (priv->poll_mode == GFAR_SQ_POLLING) {
675+
/* One Q per interrupt group: Q0 to G0, Q1 to G1 */
676+
grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
677+
grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
678+
} else { /* GFAR_MQ_POLLING */
679+
grp->rx_bit_map = rxq_mask ?
680+
*rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
681+
grp->tx_bit_map = txq_mask ?
682+
*txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
683+
}
674684
} else {
675685
grp->rx_bit_map = 0xFF;
676686
grp->tx_bit_map = 0xFF;
@@ -686,13 +696,17 @@ static int gfar_parse_group(struct device_node *np,
686696
* also assign queues to groups
687697
*/
688698
for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
699+
if (!grp->rx_queue)
700+
grp->rx_queue = priv->rx_queue[i];
689701
grp->num_rx_queues++;
690702
grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
691703
priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
692704
priv->rx_queue[i]->grp = grp;
693705
}
694706

695707
for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
708+
if (!grp->tx_queue)
709+
grp->tx_queue = priv->tx_queue[i];
696710
grp->num_tx_queues++;
697711
grp->tstat |= (TSTAT_CLEAR_THALT >> i);
698712
priv->tqueue |= (TQUEUE_EN0 >> i);
@@ -723,9 +737,22 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
723737
if (!np || !of_device_is_available(np))
724738
return -ENODEV;
725739

726-
/* parse the num of tx and rx queues */
740+
/* parse the num of HW tx and rx queues */
727741
tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
728-
num_tx_qs = tx_queues ? *tx_queues : 1;
742+
rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
743+
744+
if (priv->mode == SQ_SG_MODE) {
745+
num_tx_qs = 1;
746+
num_rx_qs = 1;
747+
} else { /* MQ_MG_MODE */
748+
if (priv->poll_mode == GFAR_SQ_POLLING) {
749+
num_tx_qs = 2; /* one q per int group */
750+
num_rx_qs = 2; /* one q per int group */
751+
} else { /* GFAR_MQ_POLLING */
752+
num_tx_qs = tx_queues ? *tx_queues : 1;
753+
num_rx_qs = rx_queues ? *rx_queues : 1;
754+
}
755+
}
729756

730757
if (num_tx_qs > MAX_TX_QS) {
731758
pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
@@ -734,9 +761,6 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
734761
return -EINVAL;
735762
}
736763

737-
rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
738-
num_rx_qs = rx_queues ? *rx_queues : 1;
739-
740764
if (num_rx_qs > MAX_RX_QS) {
741765
pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
742766
num_rx_qs, MAX_RX_QS);
@@ -777,13 +801,15 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
777801
/* Parse and initialize group specific information */
778802
if (of_device_is_compatible(np, "fsl,etsec2")) {
779803
priv->mode = MQ_MG_MODE;
804+
priv->poll_mode = GFAR_SQ_POLLING;
780805
for_each_child_of_node(np, child) {
781806
err = gfar_parse_group(child, priv, model);
782807
if (err)
783808
goto err_grp_init;
784809
}
785810
} else {
786811
priv->mode = SQ_SG_MODE;
812+
priv->poll_mode = GFAR_SQ_POLLING;
787813
err = gfar_parse_group(np, priv, model);
788814
if (err)
789815
goto err_grp_init;
@@ -1263,13 +1289,13 @@ static int gfar_probe(struct platform_device *ofdev)
12631289
dev->ethtool_ops = &gfar_ethtool_ops;
12641290

12651291
/* Register for napi ...We are registering NAPI for each grp */
1266-
if (priv->mode == SQ_SG_MODE) {
1267-
netif_napi_add(dev, &priv->gfargrp[0].napi_rx, gfar_poll_rx_sq,
1268-
GFAR_DEV_WEIGHT);
1269-
netif_napi_add(dev, &priv->gfargrp[0].napi_tx, gfar_poll_tx_sq,
1270-
2);
1271-
} else {
1272-
for (i = 0; i < priv->num_grps; i++) {
1292+
for (i = 0; i < priv->num_grps; i++) {
1293+
if (priv->poll_mode == GFAR_SQ_POLLING) {
1294+
netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1295+
gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1296+
netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1297+
gfar_poll_tx_sq, 2);
1298+
} else {
12731299
netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
12741300
gfar_poll_rx, GFAR_DEV_WEIGHT);
12751301
netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
@@ -2819,7 +2845,7 @@ static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
28192845
struct gfar_priv_grp *gfargrp =
28202846
container_of(napi, struct gfar_priv_grp, napi_rx);
28212847
struct gfar __iomem *regs = gfargrp->regs;
2822-
struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2848+
struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
28232849
int work_done = 0;
28242850

28252851
/* Clear IEVENT, so interrupts aren't called again
@@ -2850,7 +2876,7 @@ static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
28502876
struct gfar_priv_grp *gfargrp =
28512877
container_of(napi, struct gfar_priv_grp, napi_tx);
28522878
struct gfar __iomem *regs = gfargrp->regs;
2853-
struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2879+
struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
28542880
u32 imask;
28552881

28562882
/* Clear IEVENT, so interrupts aren't called again

drivers/net/ethernet/freescale/gianfar.h

Lines changed: 31 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -412,7 +412,9 @@ extern const char gfar_driver_version[];
412412

413413
/* This default RIR value directly corresponds
414414
* to the 3-bit hash value generated */
415-
#define DEFAULT_RIR0 0x05397700
415+
#define DEFAULT_8RXQ_RIR0 0x05397700
416+
/* Map even hash values to Q0, and odd ones to Q1 */
417+
#define DEFAULT_2RXQ_RIR0 0x04104100
416418

417419
/* RQFCR register bits */
418420
#define RQFCR_GPI 0x80000000
@@ -907,6 +909,22 @@ enum {
907909
MQ_MG_MODE
908910
};
909911

912+
/* GFAR_SQ_POLLING: Single Queue NAPI polling mode
913+
* The driver supports a single pair of RX/Tx queues
914+
* per interrupt group (Rx/Tx int line). MQ_MG mode
915+
* devices have 2 interrupt groups, so the device will
916+
* have a total of 2 Tx and 2 Rx queues in this case.
917+
* GFAR_MQ_POLLING: Multi Queue NAPI polling mode
918+
* The driver supports all the 8 Rx and Tx HW queues
919+
* each queue mapped by the Device Tree to one of
920+
* the 2 interrupt groups. This mode implies significant
921+
* processing overhead (CPU and controller level).
922+
*/
923+
enum gfar_poll_mode {
924+
GFAR_SQ_POLLING = 0,
925+
GFAR_MQ_POLLING
926+
};
927+
910928
/*
911929
* Per TX queue stats
912930
*/
@@ -1016,17 +1034,20 @@ struct gfar_irqinfo {
10161034
*/
10171035

10181036
struct gfar_priv_grp {
1019-
spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
1037+
spinlock_t grplock __aligned(SMP_CACHE_BYTES);
10201038
struct napi_struct napi_rx;
10211039
struct napi_struct napi_tx;
1022-
struct gfar_private *priv;
10231040
struct gfar __iomem *regs;
1024-
unsigned int rstat;
1025-
unsigned long num_rx_queues;
1026-
unsigned long rx_bit_map;
1041+
struct gfar_priv_tx_q *tx_queue;
1042+
struct gfar_priv_rx_q *rx_queue;
10271043
unsigned int tstat;
1044+
unsigned int rstat;
1045+
1046+
struct gfar_private *priv;
10281047
unsigned long num_tx_queues;
10291048
unsigned long tx_bit_map;
1049+
unsigned long num_rx_queues;
1050+
unsigned long rx_bit_map;
10301051

10311052
struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
10321053
};
@@ -1056,15 +1077,14 @@ enum gfar_dev_state {
10561077
* the buffer descriptor determines the actual condition.
10571078
*/
10581079
struct gfar_private {
1059-
unsigned int num_rx_queues;
1060-
10611080
struct device *dev;
10621081
struct net_device *ndev;
10631082
enum gfar_errata errata;
10641083
unsigned int rx_buffer_size;
10651084

10661085
u16 uses_rxfcb;
10671086
u16 padding;
1087+
u32 device_flags;
10681088

10691089
/* HW time stamping enabled flag */
10701090
int hwts_rx_en;
@@ -1075,10 +1095,11 @@ struct gfar_private {
10751095
struct gfar_priv_grp gfargrp[MAXGROUPS];
10761096

10771097
unsigned long state;
1078-
u32 device_flags;
10791098

1080-
unsigned int mode;
1099+
unsigned short mode;
1100+
unsigned short poll_mode;
10811101
unsigned int num_tx_queues;
1102+
unsigned int num_rx_queues;
10821103
unsigned int num_grps;
10831104

10841105
/* Network Statistics */

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