@@ -190,6 +190,16 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
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};
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int i , j ;
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+ /*
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+ * STMPE1600: to be able to get IRQ from pins,
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+ * a read must be done on GPMR register, or a write in
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+ * GPSR or GPCR registers
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+ */
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+ if (stmpe -> partnum == STMPE1600 ) {
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+ stmpe_reg_read (stmpe , stmpe -> regs [STMPE_IDX_GPMR_LSB ]);
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+ stmpe_reg_read (stmpe , stmpe -> regs [STMPE_IDX_GPMR_CSB ]);
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+ }
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+
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for (i = 0 ; i < CACHE_NR_REGS ; i ++ ) {
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/* STMPE801 and STMPE1600 don't have RE and FE registers */
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if ((stmpe -> partnum == STMPE801 ||
@@ -227,21 +237,11 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
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struct stmpe_gpio * stmpe_gpio = gpiochip_get_data (gc );
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- struct stmpe * stmpe = stmpe_gpio -> stmpe ;
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int offset = d -> hwirq ;
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int regoffset = offset / 8 ;
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int mask = BIT (offset % 8 );
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stmpe_gpio -> regs [REG_IE ][regoffset ] |= mask ;
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-
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- /*
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- * STMPE1600 workaround: to be able to get IRQ from pins,
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- * a read must be done on GPMR register, or a write in
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- * GPSR or GPCR registers
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- */
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- if (stmpe -> partnum == STMPE1600 )
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- stmpe_reg_read (stmpe ,
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- stmpe -> regs [STMPE_IDX_GPMR_LSB + regoffset ]);
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}
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static void stmpe_dbg_show_one (struct seq_file * s ,
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