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crypto: qat - Intel(R) QAT driver framework
This patch adds a common infractructure that will be used by all Intel(R) QuickAssist Technology (QAT) devices. v2 - added ./drivers/crypto/qat/Kconfig and ./drivers/crypto/qat/Makefile v4 - splits common part into more, smaller patches Acked-by: John Griffin <[email protected]> Reviewed-by: Bruce W. Allan <[email protected]> Signed-off-by: Tadeusz Struk <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
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‎drivers/crypto/qat/Kconfig

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config CRYPTO_DEV_QAT
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tristate
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select CRYPTO_AEAD
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select CRYPTO_AUTHENC
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select CRYPTO_ALGAPI
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select CRYPTO_AES
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select CRYPTO_CBC
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select CRYPTO_SHA1
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select CRYPTO_SHA256
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select CRYPTO_SHA512
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config CRYPTO_DEV_QAT_DH895xCC
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tristate "Support for Intel(R) DH895xCC"
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depends on X86 && PCI
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default n
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) DH895xcc with Intel(R) QuickAssist Technology
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for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_dh895xcc.

‎drivers/crypto/qat/Makefile

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obj-$(CONFIG_CRYPTO_DEV_QAT) += qat_common/
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obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCC) += qat_dh895xcc/

‎drivers/crypto/qat/qat_common/Makefile

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obj-$(CONFIG_CRYPTO_DEV_QAT) += intel_qat.o
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intel_qat-objs := adf_cfg.o \
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adf_ctl_drv.o \
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adf_dev_mgr.o \
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adf_init.o \
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adf_accel_engine.o \
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adf_aer.o \
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adf_transport.o \
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qat_crypto.o \
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qat_algs.o \
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qat_uclo.o \
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qat_hal.o
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intel_qat-$(CONFIG_DEBUG_FS) += adf_transport_debug.o

‎drivers/crypto/qat/qat_common/adf_accel_devices.h

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/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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[email protected]
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ADF_ACCEL_DEVICES_H_
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#define ADF_ACCEL_DEVICES_H_
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#include <linux/module.h>
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#include <linux/atomic.h>
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#include <linux/list.h>
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#include <linux/proc_fs.h>
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#include "adf_cfg_common.h"
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
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#define ADF_DH895XCC_PCI_DEVICE_ID 0x435
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#define ADF_DH895XCC_PMISC_BAR 1
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#define ADF_DH895XCC_ETR_BAR 2
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#define ADF_PCI_MAX_BARS 3
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#define ADF_DEVICE_NAME_LENGTH 32
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#define ADF_ETR_MAX_RINGS_PER_BANK 16
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#define ADF_MAX_MSIX_VECTOR_NAME 16
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#define ADF_DEVICE_NAME_PREFIX "qat_"
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enum adf_accel_capabilities {
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ADF_ACCEL_CAPABILITIES_NULL = 0,
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ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
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ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
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ADF_ACCEL_CAPABILITIES_CIPHER = 4,
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ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
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ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
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ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
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ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
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};
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struct adf_bar {
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resource_size_t base_addr;
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void __iomem *virt_addr;
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resource_size_t size;
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} __packed;
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struct adf_accel_msix {
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struct msix_entry *entries;
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char **names;
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} __packed;
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struct adf_accel_pci {
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struct pci_dev *pci_dev;
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struct adf_accel_msix msix_entries;
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struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
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uint8_t revid;
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uint8_t sku;
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} __packed;
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enum dev_state {
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DEV_DOWN = 0,
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DEV_UP
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};
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enum dev_sku_info {
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DEV_SKU_1 = 0,
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DEV_SKU_2,
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DEV_SKU_3,
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DEV_SKU_4,
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DEV_SKU_UNKNOWN,
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};
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static inline const char *get_sku_info(enum dev_sku_info info)
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{
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switch (info) {
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case DEV_SKU_1:
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return "SKU1";
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case DEV_SKU_2:
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return "SKU2";
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case DEV_SKU_3:
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return "SKU3";
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case DEV_SKU_4:
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return "SKU4";
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case DEV_SKU_UNKNOWN:
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default:
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break;
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}
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return "Unknown SKU";
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}
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struct adf_hw_device_class {
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const char *name;
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const enum adf_device_type type;
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uint32_t instances;
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} __packed;
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struct adf_cfg_device_data;
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struct adf_accel_dev;
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struct adf_etr_data;
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struct adf_etr_ring_data;
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struct adf_hw_device_data {
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struct adf_hw_device_class *dev_class;
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uint32_t (*get_accel_mask)(uint32_t fuse);
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uint32_t (*get_ae_mask)(uint32_t fuse);
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uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self);
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uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self);
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uint32_t (*get_num_aes)(struct adf_hw_device_data *self);
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uint32_t (*get_num_accels)(struct adf_hw_device_data *self);
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enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
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void (*hw_arb_ring_enable)(struct adf_etr_ring_data *ring);
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void (*hw_arb_ring_disable)(struct adf_etr_ring_data *ring);
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int (*alloc_irq)(struct adf_accel_dev *accel_dev);
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void (*free_irq)(struct adf_accel_dev *accel_dev);
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void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
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const char *fw_name;
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uint32_t pci_dev_id;
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uint32_t fuses;
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uint32_t accel_capabilities_mask;
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uint16_t accel_mask;
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uint16_t ae_mask;
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uint16_t tx_rings_mask;
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uint8_t tx_rx_gap;
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uint8_t instance_id;
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uint8_t num_banks;
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uint8_t num_accel;
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uint8_t num_logical_accel;
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uint8_t num_engines;
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} __packed;
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/* CSR write macro */
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#define ADF_CSR_WR(csr_base, csr_offset, val) \
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__raw_writel(val, csr_base + csr_offset)
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/* CSR read macro */
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#define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
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#define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
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#define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
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#define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
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#define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
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#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
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#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
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struct adf_admin_comms;
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struct icp_qat_fw_loader_handle;
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struct adf_fw_loader_data {
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struct icp_qat_fw_loader_handle *fw_loader;
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const struct firmware *uof_fw;
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};
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struct adf_accel_dev {
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struct adf_etr_data *transport;
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struct adf_hw_device_data *hw_device;
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struct adf_cfg_device_data *cfg;
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struct adf_fw_loader_data *fw_loader;
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struct adf_admin_comms *admin;
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struct list_head crypto_list;
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unsigned long status;
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atomic_t ref_count;
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struct dentry *debugfs_dir;
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struct list_head list;
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struct module *owner;
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uint8_t accel_id;
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uint8_t numa_node;
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struct adf_accel_pci accel_pci_dev;
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} __packed;
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#endif

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