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Merge tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux
Pull more clock framework updates from Mike Turquette: "This contains the second half the of the clk changes for 3.16. They are simply fixes and code refactoring for the OMAP clock drivers. The sunxi clock driver changes include splitting out the one mega-driver into several smaller pieces and adding support for the A31 SoC clocks" * tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux: (25 commits) clk: sunxi: document PRCM clock compatible strings clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support clk: sun6i: Protect SDRAM gating bit clk: sun6i: Protect CPU clock clk: sunxi: Rework clock protection code clk: sunxi: Move the GMAC clock to a file of its own clk: sunxi: Move the 24M oscillator to a file of its own clk: sunxi: Remove calls to clk_put clk: sunxi: document new A31 USB clock compatible clk: sunxi: Implement A31 USB clock ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC) CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic) dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock CLK: TI: gate: add composite interface clock to OMAP2 only build ARM: OMAP2: clock: add DT boot support for cpufreq_ck CLK: TI: OMAP2: add clock init support ...
2 parents b55b390 + b640a60 commit dd1845a

30 files changed

+1836
-265
lines changed

‎Documentation/devicetree/bindings/clock/sunxi.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,12 +20,15 @@ Required properties:
2020
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
2121
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
2222
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
23+
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
2324
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
2425
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
2526
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
27+
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
2628
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
2729
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
2830
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
31+
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
2932
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
3033
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
3134
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
@@ -41,6 +44,7 @@ Required properties:
4144
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
4245
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
4346
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
47+
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
4448

4549
Required properties for all clocks:
4650
- reg : shall be the control register address for the clock.

‎Documentation/devicetree/bindings/clock/ti/apll.txt

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,18 +14,32 @@ a subtype of a DPLL [2], although a simplified one at that.
1414
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
1515

1616
Required properties:
17-
- compatible : shall be "ti,dra7-apll-clock"
17+
- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
1818
- #clock-cells : from common clock binding; shall be set to 0.
1919
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
2020
- reg : address and length of the register set for controlling the APLL.
2121
It contains the information of registers in the following order:
22-
"control" - contains the control register base address
23-
"idlest" - contains the idlest register base address
22+
"control" - contains the control register offset
23+
"idlest" - contains the idlest register offset
24+
"autoidle" - contains the autoidle register offset (OMAP2 only)
25+
- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
26+
- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
27+
- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
2428

2529
Examples:
26-
apll_pcie_ck: apll_pcie_ck@4a008200 {
30+
apll_pcie_ck: apll_pcie_ck {
2731
#clock-cells = <0>;
2832
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
29-
reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
33+
reg = <0x021c>, <0x0220>;
3034
compatible = "ti,dra7-apll-clock";
3135
};
36+
37+
apll96_ck: apll96_ck {
38+
#clock-cells = <0>;
39+
compatible = "ti,omap2-apll-clock";
40+
clocks = <&sys_ck>;
41+
ti,bit-shift = <2>;
42+
ti,idlest-shift = <8>;
43+
ti,clock-frequency = <96000000>;
44+
reg = <0x0500>, <0x0530>, <0x0520>;
45+
};

‎Documentation/devicetree/bindings/clock/ti/dpll.txt

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,12 +24,14 @@ Required properties:
2424
"ti,omap4-dpll-core-clock",
2525
"ti,omap4-dpll-m4xen-clock",
2626
"ti,omap4-dpll-j-type-clock",
27+
"ti,omap5-mpu-dpll-clock",
2728
"ti,am3-dpll-no-gate-clock",
2829
"ti,am3-dpll-j-type-clock",
2930
"ti,am3-dpll-no-gate-j-type-clock",
3031
"ti,am3-dpll-clock",
3132
"ti,am3-dpll-core-clock",
3233
"ti,am3-dpll-x2-clock",
34+
"ti,omap2-dpll-core-clock",
3335

3436
- #clock-cells : from common clock binding; shall be set to 0.
3537
- clocks : link phandles of parent clocks, first entry lists reference clock
@@ -41,6 +43,7 @@ Required properties:
4143
"mult-div1" - contains the multiplier / divider register base address
4244
"autoidle" - contains the autoidle register base address (optional)
4345
ti,am3-* dpll types do not have autoidle register
46+
ti,omap2-* dpll type does not support idlest / autoidle registers
4447

4548
Optional properties:
4649
- DPLL mode setting - defining any one or more of the following overrides
@@ -73,3 +76,10 @@ Examples:
7376
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
7477
reg = <0x90>, <0x5c>, <0x68>;
7578
};
79+
80+
dpll_ck: dpll_ck {
81+
#clock-cells = <0>;
82+
compatible = "ti,omap2-dpll-core-clock";
83+
clocks = <&sys_ck>, <&sys_ck>;
84+
reg = <0x0500>, <0x0540>;
85+
};

‎Documentation/devicetree/bindings/clock/ti/dra7-atl.txt

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
1+
Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
2+
3+
The ATL IP is used to generate clock to be used to synchronize baseband and
4+
audio codec. A single ATL IP provides four ATL clock instances sharing the same
5+
functional clock but can be configured to provide different clocks.
6+
ATL can maintain a clock averages to some desired frequency based on the bws/aws
7+
signals - can compensate the drift between the two ws signal.
8+
9+
In order to provide the support for ATL and it's output clocks (which can be used
10+
internally within the SoC or external components) two sets of bindings is needed:
11+
12+
Clock tree binding:
13+
This binding uses the common clock binding[1].
14+
To be able to integrate the ATL clocks with DT clock tree.
15+
Provides ccf level representation of the ATL clocks to be used by drivers.
16+
Since the clock instances are part of a single IP this binding is used as a node
17+
for the DT clock tree, the IP driver is needed to handle the actual configuration
18+
of the IP.
19+
20+
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
21+
22+
Required properties:
23+
- compatible : shall be "ti,dra7-atl-clock"
24+
- #clock-cells : from common clock binding; shall be set to 0.
25+
- clocks : link phandles to functional clock of ATL
26+
27+
Binding for the IP driver:
28+
This binding is used to configure the IP driver which is going to handle the
29+
configuration of the IP for the ATL clock instances.
30+
31+
Required properties:
32+
- compatible : shall be "ti,dra7-atl"
33+
- reg : base address for the ATL IP
34+
- ti,provided-clocks : List of phandles to the clocks associated with the ATL
35+
- clocks : link phandles to functional clock of ATL
36+
- clock-names : Shall be set to "fck"
37+
- ti,hwmods : Shall be set to "atl"
38+
39+
Optional properties:
40+
Configuration of ATL instances:
41+
- atl{0/1/2/3} {
42+
- bws : Baseband word select signal selection
43+
- aws : Audio word select signal selection
44+
};
45+
46+
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
47+
file.
48+
49+
Examples:
50+
/* clock bindings for atl provided clocks */
51+
atl_clkin0_ck: atl_clkin0_ck {
52+
#clock-cells = <0>;
53+
compatible = "ti,dra7-atl-clock";
54+
clocks = <&atl_gfclk_mux>;
55+
};
56+
57+
atl_clkin1_ck: atl_clkin1_ck {
58+
#clock-cells = <0>;
59+
compatible = "ti,dra7-atl-clock";
60+
clocks = <&atl_gfclk_mux>;
61+
};
62+
63+
atl_clkin2_ck: atl_clkin2_ck {
64+
#clock-cells = <0>;
65+
compatible = "ti,dra7-atl-clock";
66+
clocks = <&atl_gfclk_mux>;
67+
};
68+
69+
atl_clkin3_ck: atl_clkin3_ck {
70+
#clock-cells = <0>;
71+
compatible = "ti,dra7-atl-clock";
72+
clocks = <&atl_gfclk_mux>;
73+
};
74+
75+
/* binding for the IP */
76+
atl: atl@4843c000 {
77+
compatible = "ti,dra7-atl";
78+
reg = <0x4843c000 0x3ff>;
79+
ti,hwmods = "atl";
80+
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
81+
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
82+
clocks = <&atl_gfclk_mux>;
83+
clock-names = "fck";
84+
status = "disabled";
85+
};
86+
87+
#include <dt-bindings/clk/ti-dra7-atl.h>
88+
89+
&atl {
90+
status = "okay";
91+
92+
atl2 {
93+
bws = <DRA7_ATL_WS_MCASP2_FSX>;
94+
aws = <DRA7_ATL_WS_MCASP3_FSX>;
95+
};
96+
};

‎Documentation/devicetree/bindings/clock/ti/gate.txt

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,11 @@ Required properties:
2525
to map clockdomains properly
2626
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
2727
required for a hardware errata
28+
"ti,composite-gate-clock" - composite gate clock, to be part of composite
29+
clock
30+
"ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
31+
for clock to be active before returning
32+
from clk_enable()
2833
- #clock-cells : from common clock binding; shall be set to 0
2934
- clocks : link to phandle of parent clock
3035
- reg : offset for register controlling adjustable gate, not needed for
@@ -41,7 +46,7 @@ Examples:
4146
#clock-cells = <0>;
4247
compatible = "ti,gate-clock";
4348
clocks = <&core_96m_fck>;
44-
reg = <0x48004a00 0x4>;
49+
reg = <0x0a00>;
4550
ti,bit-shift = <25>;
4651
};
4752

@@ -57,15 +62,15 @@ Examples:
5762
#clock-cells = <0>;
5863
compatible = "ti,dss-gate-clock";
5964
clocks = <&dpll4_m4x2_ck>;
60-
reg = <0x48004e00 0x4>;
65+
reg = <0x0e00>;
6166
ti,bit-shift = <0>;
6267
};
6368

6469
emac_ick: emac_ick@4800259c {
6570
#clock-cells = <0>;
6671
compatible = "ti,am35xx-gate-clock";
6772
clocks = <&ipss_ick>;
68-
reg = <0x4800259c 0x4>;
73+
reg = <0x059c>;
6974
ti,bit-shift = <1>;
7075
};
7176

@@ -80,6 +85,22 @@ Examples:
8085
compatible = "ti,hsdiv-gate-clock";
8186
clocks = <&dpll4_m2x2_mul_ck>;
8287
ti,bit-shift = <0x1b>;
83-
reg = <0x48004d00 0x4>;
88+
reg = <0x0d00>;
8489
ti,set-bit-to-disable;
8590
};
91+
92+
vlynq_gate_fck: vlynq_gate_fck {
93+
#clock-cells = <0>;
94+
compatible = "ti,composite-gate-clock";
95+
clocks = <&core_ck>;
96+
ti,bit-shift = <3>;
97+
reg = <0x0200>;
98+
};
99+
100+
sys_clkout2_src_gate: sys_clkout2_src_gate {
101+
#clock-cells = <0>;
102+
compatible = "ti,composite-no-wait-gate-clock";
103+
clocks = <&core_ck>;
104+
ti,bit-shift = <15>;
105+
reg = <0x0070>;
106+
};

‎Documentation/devicetree/bindings/clock/ti/interface.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,8 @@ Required properties:
2121
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
2222
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
2323
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
24+
"ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
25+
handling
2426
- #clock-cells : from common clock binding; shall be set to 0
2527
- clocks : link to phandle of parent clock
2628
- reg : base address for the control register

‎arch/arm/boot/dts/dra7xx-clocks.dtsi

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
clock-frequency = <0>;
2727
};
2828

29-
atlclkin3_ck: atlclkin3_ck {
29+
atl_clkin3_ck: atl_clkin3_ck {
3030
#clock-cells = <0>;
3131
compatible = "fixed-clock";
3232
clock-frequency = <0>;
@@ -277,7 +277,7 @@
277277

278278
dpll_mpu_ck: dpll_mpu_ck {
279279
#clock-cells = <0>;
280-
compatible = "ti,omap4-dpll-clock";
280+
compatible = "ti,omap5-mpu-dpll-clock";
281281
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
282282
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
283283
};
@@ -730,15 +730,15 @@
730730
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
731731
#clock-cells = <0>;
732732
compatible = "ti,mux-clock";
733-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
733+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
734734
ti,bit-shift = <28>;
735735
reg = <0x0550>;
736736
};
737737

738738
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
739739
#clock-cells = <0>;
740740
compatible = "ti,mux-clock";
741-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
741+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
742742
ti,bit-shift = <24>;
743743
reg = <0x0550>;
744744
};
@@ -1639,15 +1639,15 @@
16391639
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
16401640
#clock-cells = <0>;
16411641
compatible = "ti,mux-clock";
1642-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1642+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
16431643
ti,bit-shift = <28>;
16441644
reg = <0x1860>;
16451645
};
16461646

16471647
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
16481648
#clock-cells = <0>;
16491649
compatible = "ti,mux-clock";
1650-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1650+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
16511651
ti,bit-shift = <24>;
16521652
reg = <0x1860>;
16531653
};
@@ -1663,7 +1663,7 @@
16631663
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
16641664
#clock-cells = <0>;
16651665
compatible = "ti,mux-clock";
1666-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1666+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
16671667
ti,bit-shift = <24>;
16681668
reg = <0x1868>;
16691669
};
@@ -1679,7 +1679,7 @@
16791679
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
16801680
#clock-cells = <0>;
16811681
compatible = "ti,mux-clock";
1682-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1682+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
16831683
ti,bit-shift = <24>;
16841684
reg = <0x1898>;
16851685
};
@@ -1695,7 +1695,7 @@
16951695
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
16961696
#clock-cells = <0>;
16971697
compatible = "ti,mux-clock";
1698-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1698+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
16991699
ti,bit-shift = <24>;
17001700
reg = <0x1878>;
17011701
};
@@ -1711,7 +1711,7 @@
17111711
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
17121712
#clock-cells = <0>;
17131713
compatible = "ti,mux-clock";
1714-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1714+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
17151715
ti,bit-shift = <24>;
17161716
reg = <0x1904>;
17171717
};
@@ -1727,7 +1727,7 @@
17271727
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
17281728
#clock-cells = <0>;
17291729
compatible = "ti,mux-clock";
1730-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1730+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
17311731
ti,bit-shift = <24>;
17321732
reg = <0x1908>;
17331733
};
@@ -1743,7 +1743,7 @@
17431743
mcasp8_ahclk_mux: mcasp8_ahclk_mux {
17441744
#clock-cells = <0>;
17451745
compatible = "ti,mux-clock";
1746-
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1746+
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
17471747
ti,bit-shift = <22>;
17481748
reg = <0x1890>;
17491749
};

‎arch/arm/boot/dts/omap54xx-clocks.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@
335335

336336
dpll_mpu_ck: dpll_mpu_ck {
337337
#clock-cells = <0>;
338-
compatible = "ti,omap4-dpll-clock";
338+
compatible = "ti,omap5-mpu-dpll-clock";
339339
clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
340340
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
341341
};

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