File tree 1 file changed +3
-3
lines changed 1 file changed +3
-3
lines changed Original file line number Diff line number Diff line change 62
62
#define MIE (1 << 3) /* master if enable */
63
63
#define TSBE (1 << 2)
64
64
#define FSB (1 << 1) /* force stop bit */
65
- #define ESG (1 << 0) /* en startbit gen */
65
+ #define ESG (1 << 0) /* enable start bit gen */
66
66
67
67
/* ICSSR (also for ICSIER) */
68
68
#define GCAR (1 << 6) /* general call received */
@@ -331,7 +331,7 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
331
331
332
332
rcar_i2c_write (priv , ICMAR , (priv -> msg -> addr << 1 ) | read );
333
333
/*
334
- * We don't have a testcase but the HW engineers say that the write order
334
+ * We don't have a test case but the HW engineers say that the write order
335
335
* of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
336
336
* it didn't cause a drawback for me, let's rather be safe than sorry.
337
337
*/
@@ -489,7 +489,7 @@ static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
489
489
490
490
/*
491
491
* Try to use DMA to transmit the rest of the data if
492
- * address transfer pashe just finished.
492
+ * address transfer phase just finished.
493
493
*/
494
494
if (msr & MAT )
495
495
rcar_i2c_dma (priv );
You can’t perform that action at this time.
0 commit comments