configure: error: cannot compute suffix of object files: cannot compile

[ahmdotm]

I faced this error while trying to add new instruction. The instruction will follow the same format of fmadd.
{"mod.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_MOD_S|MASK_RM, MASK_MOD_S|MASK_RM, match_opcode, 0 },
{"mod.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_MOD_S, MASK_MOD_S, match_opcode, 0 },

and the mask the mast and match is
#define MATCH_MOD_S 0x7f
#define MASK_MOD_S 0x600007f
any idea why i am facing this error?

[pz9115]

Can you check the config.log file in riscv-gnu-toolchain folder, and list the error details here, thanks.

[TommyMurphyTM1234]

Please describe all steps needed to reproduce this from scratch and capture and attach your failing build log. That's all steps from the initial git clone, to configure, to any changes that you make to the sources, to the make command.

This error can occur if you haven't done a clean build - e.g.: make distclean && rm -rf <prefix-dir> && make 2>&1 | tee build.log - or you've configured the toolchain incorrectly. There may be other causes which are covered in existing open or closed issues:

• https://github.com/riscv-collab/riscv-gnu-toolchain/issues?q=is%3Aissue+cannot+compute+suffix+

This issue explains how to successfully add a simple custom instruction to the toolchain so there's obviously nothing wrong with the toolchain from that point of view:

• question about adding "mod" instruction in toolchain #1469 (comment)

[ahmdotm]

Hello,
after cloning into the repo:
git clone https://github.com/riscv/riscv-gnu-toolchain
then cloning into:
git clone https://github.com/riscv/riscv-opcodes
and add
cust_one rd rs1 rs2 rs3 rm 26..25=1 6..2=0x0f 1..0=3
and got the mask and match along with DECLARE_INSN and put them in riscv-opc.h
and then add
"cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_CUST_ONE|MASK_RM, MASK_CUST_ONE|MASK_RM, match_opcode, 0 },
{"cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_CUST_ONE, MASK_CUST_ONE, match_opcode, 0 },
to riscv-opc.c
and then cd path/to/riscv-gnu-toolchain
make clean
./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d
make
the config.log file have these errors
gcc: error: unrecognized command-line option '-V'
gcc: fatal error: no input files
compilation terminated.
configure:2250: $? = 1
configure:2239: gcc -qversion >&5
gcc: error: unrecognized command-line option '-qversion'; did you mean '--version'?
gcc: fatal error: no input files

but this error is not related and i think its not even the reason for terminating the process.
What I am actually trying to do is to add new instruction that takes 3 operands and have func3[14:12] and m[26:25], m here is a control signal. so the assembly code should look like this
new_inst Rd,R1,R2,R3,m
and the func3 should control the function.
I couldnt make such thing so I used the most near one that can work for me which is f extension something like fmadd.
thanks in advance.
-othman

[pz9115]

It seems you environment need a default gcc to do the make task, please check if you have install the Prerequisites in README mentioned.

[ahmdotm]

Yes I already did. I am using the toolchain for other cores without any issue. Also when I add a new instruction to INSN_CLASS_I class it work fine. but when i try to add new instruction to INSN_CLASS_F_INX class here i face the issue. I need to add the instruction as described up but I class dont have m and R3. Actually if you can help me to add new_inst Rd,R1,R2,R3,m
exactly as i described that would be nice. It can be in different class.

[TommyMurphyTM1234]

Hello, after cloning into the repo: git clone https://github.com/riscv/riscv-gnu-toolchain then cloning into: git clone https://github.com/riscv/riscv-opcodes and add cust_one rd rs1 rs2 rs3 rm 26..25=1 6..2=0x0f 1..0=3 and got the mask and match along with DECLARE_INSN and put them in riscv-opc.h and then add "cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_CUST_ONE|MASK_RM, MASK_CUST_ONE|MASK_RM, match_opcode, 0 }, {"cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_CUST_ONE, MASK_CUST_ONE, match_opcode, 0 }, to riscv-opc.c and then cd path/to/riscv-gnu-toolchain make clean ./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d make the config.log file have these errors gcc: error: unrecognized command-line option '-V' gcc: fatal error: no input files compilation terminated. configure:2250: $? = 1 configure:2239: gcc -qversion >&5 gcc: error: unrecognized command-line option '-qversion'; did you mean '--version'? gcc: fatal error: no input files

but this error is not related and i think its not even the reason for terminating the process. What I am actually trying to do is to add new instruction that takes 3 operands and have func3[14:12] and m[26:25], m here is a control signal. so the assembly code should look like this new_inst Rd,R1,R2,R3,m and the func3 should control the function. I couldnt make such thing so I used the most near one that can work for me which is f extension something like fmadd. thanks in advance. -othman

Does the toolchain build for you ok if you don't make any changes to add custom instructions?

[ahmdotm]

Hello, after cloning into the repo: git clone https://github.com/riscv/riscv-gnu-toolchain then cloning into: git clone https://github.com/riscv/riscv-opcodes and add cust_one rd rs1 rs2 rs3 rm 26..25=1 6..2=0x0f 1..0=3 and got the mask and match along with DECLARE_INSN and put them in riscv-opc.h and then add "cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_CUST_ONE|MASK_RM, MASK_CUST_ONE|MASK_RM, match_opcode, 0 }, {"cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_CUST_ONE, MASK_CUST_ONE, match_opcode, 0 }, to riscv-opc.c and then cd path/to/riscv-gnu-toolchain make clean ./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d make the config.log file have these errors gcc: error: unrecognized command-line option '-V' gcc: fatal error: no input files compilation terminated. configure:2250: $? = 1 configure:2239: gcc -qversion >&5 gcc: error: unrecognized command-line option '-qversion'; did you mean '--version'? gcc: fatal error: no input files
but this error is not related and i think its not even the reason for terminating the process. What I am actually trying to do is to add new instruction that takes 3 operands and have func3[14:12] and m[26:25], m here is a control signal. so the assembly code should look like this new_inst Rd,R1,R2,R3,m and the func3 should control the function. I couldnt make such thing so I used the most near one that can work for me which is f extension something like fmadd. thanks in advance. -othman

Does the toolchain build for you ok if you don't make any changes to add custom instructions?

Yes it work fine. And as I said when i added I class new instruction it also worked. Its just the f class that didnt work for me. i mean the format new_inst Rd,R1,R2,R3,m that i want to add. I added normal new_inst Rd,R1,R2 and it worked.

[ahmdotm]

Hello, after cloning into the repo: git clone https://github.com/riscv/riscv-gnu-toolchain then cloning into: git clone https://github.com/riscv/riscv-opcodes and add cust_one rd rs1 rs2 rs3 rm 26..25=1 6..2=0x0f 1..0=3 and got the mask and match along with DECLARE_INSN and put them in riscv-opc.h and then add "cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_CUST_ONE|MASK_RM, MASK_CUST_ONE|MASK_RM, match_opcode, 0 }, {"cust_one", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_CUST_ONE, MASK_CUST_ONE, match_opcode, 0 }, to riscv-opc.c and then cd path/to/riscv-gnu-toolchain make clean ./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d make the config.log file have these errors gcc: error: unrecognized command-line option '-V' gcc: fatal error: no input files compilation terminated. configure:2250: $? = 1 configure:2239: gcc -qversion >&5 gcc: error: unrecognized command-line option '-qversion'; did you mean '--version'? gcc: fatal error: no input files
but this error is not related and i think its not even the reason for terminating the process. What I am actually trying to do is to add new instruction that takes 3 operands and have func3[14:12] and m[26:25], m here is a control signal. so the assembly code should look like this new_inst Rd,R1,R2,R3,m and the func3 should control the function. I couldnt make such thing so I used the most near one that can work for me which is f extension something like fmadd. thanks in advance. -othman

Does the toolchain build for you ok if you don't make any changes to add custom instructions?

What I am actually trying to do is to add new instruction that takes 3 operands and have func3[14:12] and m[26:25], m here is a control signal. so the assembly code should look like this
new_inst Rd,R1,R2,R3,m
and the func3 should control the function.

[TommyMurphyTM1234]

but when i try to add new instruction to INSN_CLASS_F_INX class here i face the issue.

Does this issue help at all?

• fails build with 'configure: error' #1485

[ahmdotm]

but when i try to add new instruction to INSN_CLASS_F_INX class here i face the issue.

Does this issue help at all?

• fails build with 'configure: error' #1485

It helped but how can I test the new instruction. I tried this code:
#include <stdio.h>

// Function to use the custom instruction
int custom_instruction(int x1, int x2, int x3, int imm) {
int result;
asm volatile (
"custom %0, %1, %2, %3, %4\n\t" // Replace 'custom' with your actual instruction mnemonic
: [out] "=r" (result) // Output operand
: [in1] "r" (x1), [in2] "r" (x2), [in3] "r" (x3), [imm] "i" (imm) // Input operands
: // No clobbered registers
);
return result;
}

int main() {
int x1 = 5;
int x2 = 2;
int x3 = 3;
int imm = 1; // Example immediate value
int result;

// Call the custom instruction function
result = custom_instruction(x1, x2, x3, imm);

}
but I got with the imm
costum.c:6:5: error: impossible constraint in 'asm'
and when i remove the imm
costum.c:13: Error: illegal operands `custom a5,a5,a4,a3'
Does D class have a specific way of writing in C or assembly.
and for {"custom", 0, INSN_CLASS_D_INX, "d,s,t,r,m", MATCH_CUSTOM, MASK_CUSTOM, match_opcode, 0 }, //cust
the m here represent the imm value or the rm value?

[TommyMurphyTM1234]

You need to figure out what's wrong with your code and its use of inline assembly. You probably need to read the GCC inline assembly documentation carefully.

• https://gcc.gnu.org/onlinedocs/gcc/Using-Assembly-Language-with-C.html

[ahmdotm]

assembly documentation carefully

the code works fine with fmadd.s but not the new instruction even tho i build them the same.
and if i want to add new things beside
switch (c)
{
case 's':
INSERT_OPERAND (RS1, *ip, regno);
break;
case 'd':
INSERT_OPERAND (RD, *ip, regno);
break;
case 't':
INSERT_OPERAND (RS2, *ip, regno);
break;
case 'r':
INSERT_OPERAND (RS3, *ip, regno);
break;
}
continue;
like an imm[26:25] or call it any name like m2 where should i do that. and can I define an instruction that takes 3 reg as input rs1,rs2,rs3 and output rs3 along with the imm in I class.
how can I do this.
thanks in advance

[ahmdotm]

and what is the different between INSERT_OPERAND (RS1, *ip, regno); USE_BITS (OP_MASK_RS2, OP_SH_RS2) and INSERT_OPERAND (RS1, insn, va_arg (args, int));

[TommyMurphyTM1234]

and what is the different between INSERT_OPERAND (RS1, *ip, regno); USE_BITS (OP_MASK_RS2, OP_SH_RS2) and INSERT_OPERAND (RS1, insn, va_arg (args, int));

I don't think that this stuff is RISC-V specific and you might get better help on it in a GCC forum such as one of the mailing lists.

• https://gcc.gnu.org/lists.html

[ahmdotm]

and what is the different between INSERT_OPERAND (RS1, *ip, regno); USE_BITS (OP_MASK_RS2, OP_SH_RS2) and INSERT_OPERAND (RS1, insn, va_arg (args, int));

I don't think that this stuff is RISC-V specific and you might get better help on it in a GCC forum such as one of the mailing lists.

• https://gcc.gnu.org/lists.html

Thanks a lot Tommy

[TommyMurphyTM1234]

Closing due to lack of activity.
Reopen with additional info if necessary.