Empty default exception handler

[robamu]

The current default handlers use semihosting.
What do you think about making them as simple as possible by just doing a nop loop?
Semihosting support might not work for all use-cases. For example, I am not fully sure whether I can make it
work for my Zynq7000 based board.

[jonathanpallant]

That's a fair point - semihosting isn't a good default for everyone. They should be empty by default, but we should have examples of how to write better ones.

[jonathanpallant]

I think we also want a default Rust handler for all exceptions, rather than just asm ones. I think we discussed this somewhere ... Matrix?

[robamu]

They should be empty by default, but we should have examples of how to write better ones.

Maybe recommending crates like https://docs.rs/panic_rtt/latest/panic_rtt/ or https://crates.io/crates/panic-dcc in addition to more general recommendation like persistent logging mechanism + (soft) reboot for production apps in the docs?

I think we also want a default Rust handler for all exceptions, rather than just asm ones. I think we discussed this somewhere ... Matrix?

I implemented ASM handlers which can be overriden for Cortex-A. They can probably be used for Cortex-R as well, but I still need to test them. The default handlers for UND, ABT and Prefetch ABT will still be the same empty default handler with a permanent loop. I implemented the ASM handler to be conformant to the ARM exception return recommendations. I don't think think they help much on a system without a full OS, but I assumed if exception return is somethin the user does not require, they will have an appropriate Rust fault handler.

[robamu]

Good news, I managed to test all the exception handlers for both Cortex-R and Cortex-A using the QEMU examples. I want to go one step further and also print the exception related registers (IFSR/DFSR) in the exception handlers inside the QEMU examples. It also builds on top of #8