Merge #88

88: v0.5.2 r=therealprof a=japaric

changes required for a new release

this commit also simplifies the examples by removing the exception handler overrides and adds an
example that overrides the exception handlers.

r? @adamgreig (chosen at random)

Co-authored-by: Jorge Aparicio <[email protected]>
Co-authored-by: Adam Greig <[email protected]>

Author: 3 people

cortex-m-rt/CHANGELOG.md

@@ -7,6 +7,23 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.5.2] - 2018-08-11
+
+### Added
+
+* A `pre_init!` macro and related functionality to run a function immediately 
+  after reset, before memory initialisation
+
+### Changed
+
+- The `entry!` and `exception!` macros now also accept a closure instead of a path.
+
+- `DefaultHandler` and `UserHardFault` now default to an infinite loop if left undefined.
+
+### Fixed
+
+* Linked script modified to correctly detect `FLASH` overflow caused by `.data`
+
 ## [v0.5.1] - 2018-05-14
 
 ### Fixed
@@ -319,30 +336,32 @@ section                size        addr
 
 Initial release
 
-[Unreleased]: https://github.com/japaric/cortex-m-rt/compare/v0.5.0...HEAD
-[v0.5.0]: https://github.com/japaric/cortex-m-rt/compare/v0.4.0...v0.3.0
-[v0.4.0]: https://github.com/japaric/cortex-m-rt/compare/v0.3.15...v0.4.0
-[v0.3.15]: https://github.com/japaric/cortex-m-rt/compare/v0.3.14...v0.3.15
-[v0.3.14]: https://github.com/japaric/cortex-m-rt/compare/v0.3.13...v0.3.14
-[v0.3.13]: https://github.com/japaric/cortex-m-rt/compare/v0.3.12...v0.3.13
-[v0.3.12]: https://github.com/japaric/cortex-m-rt/compare/v0.3.11...v0.3.12
-[v0.3.11]: https://github.com/japaric/cortex-m-rt/compare/v0.3.10...v0.3.11
-[v0.3.10]: https://github.com/japaric/cortex-m-rt/compare/v0.3.9...v0.3.10
-[v0.3.9]: https://github.com/japaric/cortex-m-rt/compare/v0.3.8...v0.3.9
-[v0.3.8]: https://github.com/japaric/cortex-m-rt/compare/v0.3.7...v0.3.8
-[v0.3.7]: https://github.com/japaric/cortex-m-rt/compare/v0.3.6...v0.3.7
-[v0.3.6]: https://github.com/japaric/cortex-m-rt/compare/v0.3.5...v0.3.6
-[v0.3.5]: https://github.com/japaric/cortex-m-rt/compare/v0.3.4...v0.3.5
-[v0.3.4]: https://github.com/japaric/cortex-m-rt/compare/v0.3.3...v0.3.4
-[v0.3.3]: https://github.com/japaric/cortex-m-rt/compare/v0.3.2...v0.3.3
-[v0.3.2]: https://github.com/japaric/cortex-m-rt/compare/v0.3.1...v0.3.2
-[v0.3.1]: https://github.com/japaric/cortex-m-rt/compare/v0.3.0...v0.3.1
-[v0.3.0]: https://github.com/japaric/cortex-m-rt/compare/v0.2.4...v0.3.0
-[v0.2.4]: https://github.com/japaric/cortex-m-rt/compare/v0.2.3...v0.2.4
-[v0.2.3]: https://github.com/japaric/cortex-m-rt/compare/v0.2.2...v0.2.3
-[v0.2.2]: https://github.com/japaric/cortex-m-rt/compare/v0.2.1...v0.2.2
-[v0.2.1]: https://github.com/japaric/cortex-m-rt/compare/v0.2.0...v0.2.1
-[v0.2.0]: https://github.com/japaric/cortex-m-rt/compare/v0.1.3...v0.2.0
-[v0.1.3]: https://github.com/japaric/cortex-m-rt/compare/v0.1.2...v0.1.3
-[v0.1.2]: https://github.com/japaric/cortex-m-rt/compare/v0.1.1...v0.1.2
-[v0.1.1]: https://github.com/japaric/cortex-m-rt/compare/v0.1.0...v0.1.1
+[Unreleased]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.2...HEAD
+[v0.5.2]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.1...v0.5.2
+[v0.5.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.5.0...v0.5.1
+[v0.5.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.4.0...v0.5.0
+[v0.4.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.15...v0.4.0
+[v0.3.15]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.14...v0.3.15
+[v0.3.14]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.13...v0.3.14
+[v0.3.13]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.12...v0.3.13
+[v0.3.12]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.11...v0.3.12
+[v0.3.11]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.10...v0.3.11
+[v0.3.10]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.9...v0.3.10
+[v0.3.9]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.8...v0.3.9
+[v0.3.8]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.7...v0.3.8
+[v0.3.7]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.6...v0.3.7
+[v0.3.6]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.5...v0.3.6
+[v0.3.5]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.4...v0.3.5
+[v0.3.4]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.3...v0.3.4
+[v0.3.3]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.2...v0.3.3
+[v0.3.2]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.1...v0.3.2
+[v0.3.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.3.0...v0.3.1
+[v0.3.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.2.4...v0.3.0
+[v0.2.4]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.2.3...v0.2.4
+[v0.2.3]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.2.2...v0.2.3
+[v0.2.2]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.2.1...v0.2.2
+[v0.2.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.2.0...v0.2.1
+[v0.2.0]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.1.3...v0.2.0
+[v0.1.3]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.1.2...v0.1.3
+[v0.1.2]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.1.1...v0.1.2
+[v0.1.1]: https://github.com/rust-embedded/cortex-m-rt/compare/v0.1.0...v0.1.1

cortex-m-rt/Cargo.toml

@@ -7,7 +7,7 @@ keywords = ["arm", "cortex-m", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m-rt"
 repository = "https://github.com/japaric/cortex-m-rt"
-version = "0.5.1"
+version = "0.5.2"
 
 [build-dependencies]
 cc = "1.0.10"
@@ -18,6 +18,7 @@ r0 = "0.2.1"
 [dev-dependencies]
 panic-semihosting = "0.3.0"
 panic-abort = "0.2.0"
+cortex-m = "0.5.4"
 
 [features]
 device = []

cortex-m-rt/ci/script.sh

@@ -9,6 +9,7 @@ main() {
         alignment
         minimal
         main
+        override-exception
         pre_init
         state
     )

cortex-m-rt/examples/alignment.rs

@@ -4,14 +4,12 @@
 #![no_main]
 #![no_std]
 
-#[macro_use(entry, exception)]
+#[macro_use(entry)]
 extern crate cortex_m_rt as rt;
 extern crate panic_abort;
 
 use core::ptr;
 
-use rt::ExceptionFrame;
-
 entry!(main);
 
 static mut BSS1: u16 = 0;
@@ -33,13 +31,3 @@ fn main() -> ! {
 
     loop {}
 }
-
-exception!(HardFault, hard_fault);
-
-fn hard_fault(_ef: &ExceptionFrame) -> ! {
-    loop {}
-}
-
-exception!(*, default_handler);
-
-fn default_handler(_irqn: i16) {}

cortex-m-rt/examples/device.rs

@@ -5,31 +5,17 @@
 #![no_main]
 #![no_std]
 
-#[macro_use(entry, exception)]
+#[macro_use(entry)]
 extern crate cortex_m_rt as rt;
 extern crate panic_semihosting;
 
-use rt::ExceptionFrame;
-
 // the program entry point
 entry!(main);
 
 fn main() -> ! {
     loop {}
 }
 
-// the hard fault handler
-exception!(HardFault, hard_fault);
-
-fn hard_fault(_ef: &ExceptionFrame) -> ! {
-    loop {}
-}
-
-// the default exception handler
-exception!(*, default_handler);
-
-fn default_handler(_irqn: i16) {}
-
 // interrupts portion of the vector table
 pub union Vector {
     handler: unsafe extern "C" fn(),

cortex-m-rt/examples/main.rs

@@ -4,25 +4,10 @@
 #![no_main]
 #![no_std]
 
-#[macro_use(exception)]
 extern crate cortex_m_rt as rt;
 extern crate panic_semihosting;
 
-use rt::ExceptionFrame;
-
 #[no_mangle]
 pub unsafe extern "C" fn main() -> ! {
     loop {}
 }
-
-// the hard fault handler
-exception!(HardFault, hard_fault);
-
-fn hard_fault(_ef: &ExceptionFrame) -> ! {
-    loop {}
-}
-
-// the default exception handler
-exception!(*, default_handler);
-
-fn default_handler(_irqn: i16) {}

cortex-m-rt/examples/minimal.rs

@@ -5,27 +5,13 @@
 #![no_main]
 #![no_std]
 
-#[macro_use(entry, exception)]
+#[macro_use(entry)]
 extern crate cortex_m_rt as rt;
 extern crate panic_semihosting;
 
-use rt::ExceptionFrame;
-
 // the program entry point
 entry!(main);
 
 fn main() -> ! {
     loop {}
 }
-
-// the hard fault handler
-exception!(HardFault, hard_fault);
-
-fn hard_fault(_ef: &ExceptionFrame) -> ! {
-    loop {}
-}
-
-// the default exception handler
-exception!(*, default_handler);
-
-fn default_handler(_irqn: i16) {}

cortex-m-rt/examples/override-exception.rs

@@ -0,0 +1,35 @@
+//! How to override the hard fault exception handler and the default exception handler
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m;
+#[macro_use(entry, exception)]
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+
+use cortex_m::asm;
+use rt::ExceptionFrame;
+
+// the program entry point
+entry!(main);
+
+fn main() -> ! {
+    loop {}
+}
+
+exception!(*, default_handler);
+
+fn default_handler(_irqn: i16) {
+    asm::bkpt();
+}
+
+exception!(HardFault, hard_fault);
+
+fn hard_fault(_ef: &ExceptionFrame) -> ! {
+    asm::bkpt();
+
+    loop {}
+}

cortex-m-rt/examples/state.rs

@@ -9,8 +9,6 @@
 extern crate cortex_m_rt as rt;
 extern crate panic_semihosting;
 
-use rt::ExceptionFrame;
-
 // the program entry point
 entry!(main);
 
@@ -24,15 +22,3 @@ exception!(SysTick, sys_tick, state: u32 = 0);
 fn sys_tick(state: &mut u32) {
     *state += 1;
 }
-
-// the hard fault handler
-exception!(HardFault, hard_fault);
-
-fn hard_fault(_ef: &ExceptionFrame) -> ! {
-    loop {}
-}
-
-// the default exception handler
-exception!(*, default_handler);
-
-fn default_handler(_irqn: i16) {}