stable by default, remove exception module, add SCB.vect_active, ..

tweak Exception enum to match CMSIS names, document the parts of the API that require opting into
`"inline-asm"`.

Author: japaric

.travis.yml

@@ -2,14 +2,33 @@ language: rust
 
 matrix:
   include:
+    - env: TARGET=x86_64-unknown-linux-gnu
+      rust: beta
+
+    - env: TARGET=thumbv6m-none-eabi
+      rust: beta
+
+    - env: TARGET=thumbv7m-none-eabi
+      rust: beta
+
+    - env: TARGET=thumbv7em-none-eabi
+      rust: beta
+
+    - env: TARGET=thumbv7em-none-eabihf
+      rust: beta
+
     - env: TARGET=x86_64-unknown-linux-gnu
       rust: nightly
+
     - env: TARGET=thumbv6m-none-eabi
       rust: nightly
+
     - env: TARGET=thumbv7m-none-eabi
       rust: nightly
+
     - env: TARGET=thumbv7em-none-eabi
       rust: nightly
+
     - env: TARGET=thumbv7em-none-eabihf
       rust: nightly
 

CHANGELOG.md

@@ -5,7 +5,29 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
-## [Unreleased]
+## [v0.5.0] - 2018-05-11
+
+### Added
+
+- `DebugMonitor` and `SecureFault` variants to the `Exception` enumeration.
+
+- An optional `"inline-asm"` feature
+
+### Changed
+
+- [breaking-change] This crate now requires `arm-none-eabi-gcc` to be installed and available in
+  `$PATH` when built with the `"inline-asm"` feature disabled (which is disabled by default).
+
+- [breaking-change] The `register::{apsr,lr,pc}` modules are now behind the `"inline-asm"` feature.
+
+- [breaking-change] Some variants of the `Exception` enumeration are no longer available on
+  `thumbv6m-none-eabi`. See API docs for details.
+
+### Removed
+
+- [breaking-change] The `exception` module has been removed. A replacement for `Exception::active`
+  can be found in `SCB::vect_active`. A modified version `exception::Exception` can be found in the
+  `peripheral::scb` module.
 
 ## [v0.4.3] - 2018-01-25
 

Cargo.toml

@@ -7,23 +7,16 @@ keywords = ["arm", "cortex-m", "register", "peripheral"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m"
 repository = "https://github.com/japaric/cortex-m"
-version = "0.4.4"
+version = "0.5.0"
 
 [build-dependencies]
 cc = "1.0.10"
 
 [dependencies]
+aligned = "0.2.0"
+bare-metal = "0.2.0"
 volatile-register = "0.2.0"
 
-[dependencies.aligned]
-default-features = false
-version = "0.1.2"
-
-[dependencies.bare-metal]
-default-features = false
-version = "0.1.2"
-
 [features]
 cm7-r0p1 = []
-default = ["inline-asm"]
 inline-asm = []

asm/nop.s

@@ -1,4 +1,3 @@
   .global __nop
 __nop:
-  nop
   bx lr

ci/script.sh

@@ -1,15 +1,25 @@
 set -euxo pipefail
 
 main() {
+    cargo check --target $TARGET
+
+    if [ $TRAVIS_RUST_VERSION = nightly ]; then
+        cargo check --target $TARGET --features inline-asm
+    fi
+
     case $TARGET in
         thumbv7em-none-eabi*)
             cargo check --target $TARGET --features cm7-r0p1
-            cargo check --target $TARGET
+
+            if [ $TRAVIS_RUST_VERSION = nightly ]; then
+                cargo check --target $TARGET --features 'cm7-r0p1 inline-asm'
+            fi
             ;;
+
         thumbv*-none-eabi*)
-            cargo check --target $TARGET
             ;;
-        *)
+
+        x86_64-unknown-linux-gnu)
             cargo test --target $TARGET
             ;;
     esac

src/exception.rs

@@ -5,11 +5,35 @@
 //! - Access to core peripherals like NVIC, SCB and SysTick.
 //! - Access to core registers like CONTROL, MSP and PSR.
 //! - Interrupt manipulation mechanisms
-//! - Safe wrappers around assembly instructions like `bkpt`
+//! - Safe wrappers around Cortex-M specific instructions like `bkpt`
+//!
+//! # Requirements
+//!
+//! To use this crate on the stable or beta channel `arm-none-eabi-gcc` needs to be installed and
+//! available in your `$PATH`.
+//!
+//! # Optional features
+//!
+//! ## `inline-asm`
+//!
+//! When this feature is enabled the implementation of all the functions inside the `asm` and
+//! `register` modules use inline assembly (`asm!`) instead of external assembly (FFI into separate
+//! assembly files compiled using `arm-none-eabi-gcc`). The advantages the enabling `inline-asm`
+//! are:
+//!
+//! - Reduced overhead. FFI eliminates the possibility of inlining so all operations include a
+//! function call overhead when `inline-asm` is not enabled.
+//!
+//! - `arm-none-eabi-gcc` is not required for building this crate.
+//!
+//! - Some of the `register` API only becomes available only when `inline-asm` is enabled. Check the
+//! API docs for details.
+//!
+//! The disadvantage is that `inline-asm` requires a nightly toolchain.
 
+#![cfg_attr(feature = "inline-asm", feature(asm))]
 #![deny(missing_docs)]
 #![deny(warnings)]
-#![cfg_attr(feature = "inline-asm", feature(asm))]
 #![no_std]
 
 extern crate aligned;
@@ -20,16 +44,11 @@ extern crate volatile_register;
 mod macros;
 
 pub mod asm;
-pub mod exception;
 pub mod interrupt;
-// NOTE(target_arch) is for documentation purposes
+// NOTE(target_arch = "x86_64") is used throughout this crate for documentation purposes
 #[cfg(any(armv7m, target_arch = "x86_64"))]
 pub mod itm;
 pub mod peripheral;
 pub mod register;
 
 pub use peripheral::Peripherals;
-
-#[cfg(feature = "singleton")]
-#[doc(hidden)]
-pub use untagged_option::UntaggedOption;

src/lib.rs

@@ -63,16 +63,19 @@ macro_rules! singleton {
                 let expr = $expr;
 
                 #[allow(unsafe_code)]
-                unsafe { VAR = Some(expr) }
+                unsafe {
+                    VAR = Some(expr)
+                }
 
                 #[allow(unsafe_code)]
-                unsafe { VAR.as_mut() }
+                unsafe {
+                    VAR.as_mut()
+                }
             }
         })
-    }
+    };
 }
 
-
 /// ``` compile_fail
 /// #[macro_use(singleton)]
 /// extern crate cortex_m;

src/macros.rs

@@ -2,8 +2,8 @@
 
 use volatile_register::{RO, RW};
 
-use peripheral::NVIC;
 use interrupt::Nr;
+use peripheral::NVIC;
 
 /// Register block
 #[repr(C)]