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Merge #88
88: make compilable on stable r=japaric a=japaric This PR makes this crate compilable on stable when the "inline-asm" and "singleton" Cargo features are disabled (they are enabled by default to maintain backwards compatibility). The main change has been replacing almost (\*) all inline `asm!` invocations with FFI calls into external assembly files. (\*) Stuff that has not been converted into external assembly file and thus is not available on stable: - Reading the (A)PSR register (I'm not sure if this will work with the extra function call overhead) - Reading and writing the Link Register (LR) - Reading and writing the Program Counter (PC) I would appreciate if someone checked that all the stuff that's now using FFI calls has the same semantics as the inline `asm!` version. Co-authored-by: Jorge Aparicio <[email protected]>
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‎.travis.yml

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@@ -3,15 +3,62 @@ language: rust
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matrix:
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include:
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- env: TARGET=x86_64-unknown-linux-gnu
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rust: nightly
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- env: TARGET=thumbv6m-none-eabi
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rust: beta
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv7m-none-eabi
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rust: beta
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv7em-none-eabi
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rust: beta
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv7em-none-eabihf
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rust: beta
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv6m-none-eabi
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rust: nightly
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv7m-none-eabi
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rust: nightly
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv7em-none-eabi
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rust: nightly
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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- env: TARGET=thumbv7em-none-eabihf
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rust: nightly
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addons:
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apt:
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packages:
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- gcc-arm-none-eabi
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before_install: set -e
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‎CHANGELOG.md

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@@ -5,7 +5,50 @@ All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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8-
## [Unreleased]
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## [v0.5.0] - 2018-05-11
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### Added
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- `DebugMonitor` and `SecureFault` variants to the `Exception` enumeration.
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- An optional `"inline-asm"` feature
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### Changed
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- [breaking-change] This crate now requires `arm-none-eabi-gcc` to be installed and available in
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`$PATH` when built with the `"inline-asm"` feature disabled (which is disabled by default).
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- [breaking-change] The `register::{apsr,lr,pc}` modules are now behind the `"inline-asm"` feature.
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- [breaking-change] Some variants of the `Exception` enumeration are no longer available on
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`thumbv6m-none-eabi`. See API docs for details.
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- [breaking-change] Several of the variants of the `Exception` enumeration have been renamed to
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match the CMSIS specification.
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- [breaking-change] fixed typo in `shcrs` field of `scb::RegisterBlock`; it was previously named
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`shpcrs`.
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- [breaking-change] removed several fields from `scb::RegisterBlock` on ARMv6-M. These registers are
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not available on that sub-architecture.
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- [breaking-change] changed the type of `scb::RegisterBlock.shpr` from `RW<u8>` to `RW<u32>` on
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ARMv6-M. These registers are word accessible only on that sub-architecture.
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- [breaking-change] renamed the `mmar` field of `scb::RegisterBlock` to `mmfar` to match the CMSIS
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name.
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- [breaking-change] removed the `iabr` field from `scb::RegisterBlock` on ARMv6-M. This register is
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not available on that sub-architecture.
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- [breaking-change] removed several fields from `cpuid::RegisterBlock` on ARMv6-M. These registers
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are not available on that sub-architecture.
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### Removed
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- [breaking-change] The `exception` module has been removed. A replacement for `Exception::active`
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can be found in `SCB::vect_active`. A modified version `exception::Exception` can be found in the
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`peripheral::scb` module.
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## [v0.4.3] - 2018-01-25
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‎Cargo.toml

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@@ -7,13 +7,16 @@ keywords = ["arm", "cortex-m", "register", "peripheral"]
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license = "MIT OR Apache-2.0"
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name = "cortex-m"
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repository = "https://github.com/japaric/cortex-m"
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version = "0.4.3"
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version = "0.5.0"
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[build-dependencies]
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cc = "1.0.10"
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[dependencies]
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aligned = "0.1.1"
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bare-metal = "0.1.0"
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aligned = "0.2.0"
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bare-metal = "0.2.0"
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volatile-register = "0.2.0"
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untagged-option = "0.1.1"
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[features]
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cm7-r0p1 = []
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inline-asm = []

‎asm/basepri_max-cm7-r0p1.s

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.global __basepri_max
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.syntax unified
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__basepri_max:
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mrs r1, PRIMASK
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cpsid i
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tst.w r1, #1
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msr BASEPRI_MAX, r0
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it ne
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bxne lr
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cpsie i
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bx lr

‎asm/basepri_max.s

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.global __basepri_max
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__basepri_max:
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msr BASEPRI_MAX, r0
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bx lr

‎asm/basepri_r.s

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.global __basepri_r
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__basepri_r:
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mrs r0, BASEPRI
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bx lr

‎asm/basepri_w-cm7-r0p1.s

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@@ -0,0 +1,11 @@
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.global __basepri_w
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.syntax unified
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__basepri_w:
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mrs r1, PRIMASK
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cpsid i
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tst.w r1, #1
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msr BASEPRI, r0
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it ne
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bxne lr
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cpsie i
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bx lr

‎asm/basepri_w.s

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.global __basepri_w
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__basepri_w:
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msr BASEPRI, r0
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bx lr

‎asm/bkpt.s

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.global __bkpt
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__bkpt:
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bkpt
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bx lr

‎asm/control.s

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.global __control
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__control:
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mrs r0, CONTROL
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bx lr

‎asm/cpsid.s

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@@ -0,0 +1,4 @@
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.global __cpsid
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__cpsid:
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cpsid i
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bx lr

‎asm/cpsie.s

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@@ -0,0 +1,4 @@
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.global __cpsie
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__cpsie:
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cpsie i
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bx lr

‎asm/dmb.s

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.global __dmb
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__dmb:
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dmb 0xF
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bx lr

‎asm/dsb.s

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@@ -0,0 +1,4 @@
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.global __dsb
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__dsb:
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dsb 0xF
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bx lr

‎asm/faultmask.s

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@@ -0,0 +1,4 @@
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.global __faultmask
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__faultmask:
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mrs r0, FAULTMASK
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bx lr

‎asm/isb.s

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.global __isb
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__isb:
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isb 0xF
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bx lr

‎asm/msp_r.s

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.global __msp_r
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__msp_r:
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mrs r0, MSP
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bx lr

‎asm/msp_w.s

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@@ -0,0 +1,4 @@
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.global __msp_w
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__msp_w:
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msr MSP, r0
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bx lr

‎asm/nop.s

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@@ -0,0 +1,3 @@
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.global __nop
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__nop:
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bx lr

‎asm/primask.s

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@@ -0,0 +1,4 @@
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.global __primask
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__primask:
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mrs r0, PRIMASK
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bx lr

‎asm/psp_r.s

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@@ -0,0 +1,4 @@
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.global __psp_r
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__psp_r:
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mrs r0, PSP
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bx lr

‎asm/psp_w.s

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@@ -0,0 +1,4 @@
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.global __psp_w
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__psp_w:
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msr PSP, r0
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bx lr

‎asm/sev.s

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@@ -0,0 +1,4 @@
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.global __sev
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__sev:
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sev
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bx lr

‎asm/wfe.s

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@@ -0,0 +1,4 @@
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.global __wfe
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__wfe:
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wfe
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bx lr

‎asm/wfi.s

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
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.global __wfi
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__wfi:
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wfi
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bx lr

‎build.rs

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@@ -1,18 +1,58 @@
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extern crate cc;
2+
13
use std::env;
24

35
fn main() {
46
let target = env::var("TARGET").unwrap();
57

8+
if target.starts_with("thumb") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() {
9+
// NOTE we need to place each routine in a separate assembly file or the linker won't be
10+
// able to discard the unused routines
11+
let mut build = cc::Build::new();
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build
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.file("asm/basepri_r.s")
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.file("asm/bkpt.s")
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.file("asm/control.s")
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.file("asm/cpsid.s")
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.file("asm/cpsie.s")
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.file("asm/dmb.s")
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.file("asm/dsb.s")
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.file("asm/faultmask.s")
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.file("asm/isb.s")
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.file("asm/msp_r.s")
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.file("asm/msp_w.s")
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.file("asm/nop.s")
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.file("asm/primask.s")
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.file("asm/psp_r.s")
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.file("asm/psp_w.s")
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.file("asm/sev.s")
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.file("asm/wfe.s")
30+
.file("asm/wfi.s");
31+
32+
if env::var_os("CARGO_FEATURE_CM7_R0P1").is_some() {
33+
build.file("asm/basepri_max-cm7-r0p1.s");
34+
build.file("asm/basepri_w-cm7-r0p1.s");
35+
} else {
36+
build.file("asm/basepri_max.s");
37+
build.file("asm/basepri_w.s");
38+
}
39+
40+
build.compile("asm");
41+
}
42+
643
if target.starts_with("thumbv6m-") {
44+
println!("cargo:rustc-cfg=cortex_m");
745
println!("cargo:rustc-cfg=armv6m");
846
} else if target.starts_with("thumbv7m-") {
47+
println!("cargo:rustc-cfg=cortex_m");
948
println!("cargo:rustc-cfg=armv7m");
1049
} else if target.starts_with("thumbv7em-") {
50+
println!("cargo:rustc-cfg=cortex_m");
1151
println!("cargo:rustc-cfg=armv7m");
1252
//println!("cargo:rustc-cfg=armv7em");
1353
}
1454

15-
if target.ends_with("eabihf") {
55+
if target.ends_with("-eabihf") {
1656
println!("cargo:rustc-cfg=has_fpu");
1757
}
1858
}

‎ci/script.sh

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@@ -1,15 +1,25 @@
11
set -euxo pipefail
22

33
main() {
4+
cargo check --target $TARGET
5+
6+
if [ $TRAVIS_RUST_VERSION = nightly ]; then
7+
cargo check --target $TARGET --features inline-asm
8+
fi
9+
410
case $TARGET in
511
thumbv7em-none-eabi*)
612
cargo check --target $TARGET --features cm7-r0p1
7-
cargo check --target $TARGET
13+
14+
if [ $TRAVIS_RUST_VERSION = nightly ]; then
15+
cargo check --target $TARGET --features 'cm7-r0p1 inline-asm'
16+
fi
817
;;
18+
919
thumbv*-none-eabi*)
10-
cargo check --target $TARGET
1120
;;
12-
*)
21+
22+
x86_64-unknown-linux-gnu)
1323
cargo test --target $TARGET
1424
;;
1525
esac

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