Vxworks riscv target specs: remove redundant zicsr feature

Author: biabbas

compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs

@@ -1,4 +1,4 @@
-use crate::spec::{base, StackProbeType, Target, TargetOptions};
+use crate::spec::{StackProbeType, Target, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
             cpu: "generic-rv32".into(),
             llvm_abiname: "ilp32d".into(),
             max_atomic_width: Some(32),
-            features: "+m,+a,+f,+d,+c,+zicsr".into(),
+            features: "+m,+a,+f,+d,+c".into(),
             stack_probes: StackProbeType::Inline,
             ..base::vxworks::opts()
         },

compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs

@@ -1,4 +1,4 @@
-use crate::spec::{base, StackProbeType, Target, TargetOptions};
+use crate::spec::{StackProbeType, Target, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
             cpu: "generic-rv64".into(),
             llvm_abiname: "lp64d".into(),
             max_atomic_width: Some(64),
-            features: "+m,+a,+f,+d,+c,+zicsr".into(),
+            features: "+m,+a,+f,+d,+c".into(),
             stack_probes: StackProbeType::Inline,
             ..base::vxworks::opts()
         },