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Commit d60d2a5

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alexcrichtonTimNN
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Merge pull request #67 from arielb1/cmov-bits
Fix computeKnownBits for ARMISD::CMOV
2 parents 13dce89 + 0ee58d3 commit d60d2a5

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+21
-2
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2 files changed

+21
-2
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lib/Target/ARM/ARMISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -11324,8 +11324,8 @@ static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
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if (Op.getOpcode() == ARMISD::CMOV) {
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APInt KZ2(KnownZero.getBitWidth(), 0);
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APInt KO2(KnownOne.getBitWidth(), 0);
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computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
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computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
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computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
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computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
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KnownZero &= KZ2;
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KnownOne &= KO2;

test/CodeGen/ARM/no-cmov2bfi.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
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; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
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declare zeroext i1 @dummy()
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define i8 @test(i8 %a1, i1 %c) {
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; CHECK-NOBFI-NOT: bfi
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; CHECK-NOBFI: bl dummy
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; CHECK-NOBFI: cmp r0, #0
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; CHECK-NOBFI: it ne
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; CHECK-NOBFI: orrne [[REG:r[0-9]+]], [[REG]], #8
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; CHECK-NOBFI: mov r0, [[REG]]
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%1 = and i8 %a1, -9
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%2 = select i1 %c, i8 %1, i8 %a1
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%3 = tail call zeroext i1 @dummy()
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%4 = or i8 %2, 8
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%ret = select i1 %3, i8 %4, i8 %2
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ret i8 %ret
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}

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