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1 parent 4fe9245 commit a1c5b5aCopy full SHA for a1c5b5a
compiler/rustc_codegen_llvm/src/context.rs
@@ -154,6 +154,11 @@ pub(crate) unsafe fn create_module<'ll>(
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// See https://github.com/llvm/llvm-project/pull/106951
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target_data_layout = target_data_layout.replace("-i128:128", "");
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}
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+ if sess.target.arch.starts_with("mips64") {
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+ // LLVM 20 updates the mips64 layout to correctly align 128 bit integers to 128 bit.
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+ // See https://github.com/llvm/llvm-project/pull/112084
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+ target_data_layout = target_data_layout.replace("-i128:128", "");
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+ }
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// Ensure the data-layout values hardcoded remain the defaults.
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