Skip to content

Commit e4c44c5

Browse files
committed
Update comments per review feedback
1 parent 92c8317 commit e4c44c5

File tree

1 file changed

+46
-10
lines changed

1 file changed

+46
-10
lines changed

library/core/src/slice/mod.rs

+46-10
Original file line numberDiff line numberDiff line change
@@ -3436,12 +3436,30 @@ impl<T> [T] {
34363436
}
34373437
}
34383438

3439-
/// Split a slice into a prefix, a middle of aligned simd types, and a suffix.
3439+
/// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix.
34403440
///
34413441
/// This is a safe wrapper around [`slice::align_to`], so has the same weak
3442-
/// preconditions as that method. Notably, you must not assume any particular
3443-
/// split between the three parts: it's legal for the middle slice to be
3444-
/// empty even if the input slice is longer than `3 * LANES`.
3442+
/// postconditions as that method. You're only assured that
3443+
/// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`.
3444+
///
3445+
/// Notably, all of the following are possible:
3446+
/// - `prefix.len() >= LANES`.
3447+
/// - `middle.is_empty()` despite `self.len() >= 3 * LANES`.
3448+
/// - `suffix.len() >= LANES`.
3449+
///
3450+
/// That said, this is a safe method, so if you're only writing safe code,
3451+
/// then this can at most cause incorrect logic, not unsoundness.
3452+
///
3453+
/// # Panics
3454+
///
3455+
/// This will panic if the size of the SIMD type is different from
3456+
/// `LANES` times that of the scalar.
3457+
///
3458+
/// At the time of writing, the trait restrictions on `Simd<T, LANES>` keeps
3459+
/// that from ever happening, as only power-of-two numbers of lanes are
3460+
/// supported. It's possible that, in the future, those restrictions might
3461+
/// be lifted in a way that would make it possible to see panics from this
3462+
/// method for something like `LANES == 3`.
34453463
///
34463464
/// # Examples
34473465
///
@@ -3491,14 +3509,32 @@ impl<T> [T] {
34913509
unsafe { self.align_to() }
34923510
}
34933511

3494-
/// Split a slice into a prefix, a middle of aligned simd types, and a suffix.
3512+
/// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix.
34953513
///
3496-
/// This is a safe wrapper around [`slice::align_to`], so has the same weak
3497-
/// preconditions as that method. Notably, you must not assume any particular
3498-
/// split between the three parts: it's legal for the middle slice to be
3499-
/// empty even if the input slice is longer than `3 * LANES`.
3514+
/// This is a safe wrapper around [`slice::align_to_mut`], so has the same weak
3515+
/// postconditions as that method. You're only assured that
3516+
/// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`.
3517+
///
3518+
/// Notably, all of the following are possible:
3519+
/// - `prefix.len() >= LANES`.
3520+
/// - `middle.is_empty()` despite `self.len() >= 3 * LANES`.
3521+
/// - `suffix.len() >= LANES`.
3522+
///
3523+
/// That said, this is a safe method, so if you're only writing safe code,
3524+
/// then this can at most cause incorrect logic, not unsoundness.
3525+
///
3526+
/// This is the mutable version of [`slice::as_simd`]; see that for examples.
3527+
///
3528+
/// # Panics
3529+
///
3530+
/// This will panic if the size of the SIMD type is different from
3531+
/// `LANES` times that of the scalar.
35003532
///
3501-
/// This is the mutable version of [`slice::as_simd`]; see that for more.
3533+
/// At the time of writing, the trait restrictions on `Simd<T, LANES>` keeps
3534+
/// that from ever happening, as only power-of-two numbers of lanes are
3535+
/// supported. It's possible that, in the future, those restrictions might
3536+
/// be lifted in a way that would make it possible to see panics from this
3537+
/// method for something like `LANES == 3`.
35023538
#[unstable(feature = "portable_simd", issue = "86656")]
35033539
#[cfg(not(miri))] // Miri does not support all SIMD intrinsics
35043540
pub fn as_simd_mut<const LANES: usize>(&mut self) -> (&mut [T], &mut [Simd<T, LANES>], &mut [T])

0 commit comments

Comments
 (0)