Add A32 support to intrinsic-test and updated missing intrinsics list

Author: Amanieu

ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile

@@ -1,13 +1,17 @@
-FROM ubuntu:18.04
+FROM ubuntu:21.10
 RUN apt-get update && apt-get install -y --no-install-recommends \
   gcc \
+  g++ \
   ca-certificates \
   libc6-dev \
   gcc-arm-linux-gnueabihf \
+  g++-arm-linux-gnueabihf \
   libc6-dev-armhf-cross \
   qemu-user \
   make \
-  file
+  file \
+  clang-13 \
+  lld
 ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \
     CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -L /usr/arm-linux-gnueabihf" \
     OBJDUMP=arm-linux-gnueabihf-objdump

ci/run.sh

@@ -37,6 +37,12 @@ case ${TARGET} in
     mips-* | mipsel-*)
 	export RUSTFLAGS="${RUSTFLAGS} -C llvm-args=-fast-isel=false"
 	;;
+    # Some of our test dependencies use the deprecated `gcc` crates which is
+    # missing a fix from https://github.com/alexcrichton/cc-rs/pull/627. Apply
+    # the workaround manually here.
+    armv7-*eabihf | thumbv7-*eabihf)
+        export TARGET_CFLAGS="-mfpu=vfpv3-d16"
+        ;;
 esac
 
 echo "RUSTFLAGS=${RUSTFLAGS}"
@@ -122,7 +128,10 @@ esac
 
 if [ "${TARGET}" = "aarch64-unknown-linux-gnu" ]; then
     export CPPFLAGS="-fuse-ld=lld -I/usr/aarch64-linux-gnu/include/ -I/usr/aarch64-linux-gnu/include/c++/9/aarch64-linux-gnu/"
-    cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- crates/intrinsic-test/acle/tools/intrinsic_db/advsimd.csv --runner "${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}" --cppcompiler "clang++-13" --skip crates/intrinsic-test/missing.txt
+    RUST_LOG=warn cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- crates/intrinsic-test/acle/tools/intrinsic_db/advsimd.csv --runner "${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}" --cppcompiler "clang++-13" --skip crates/intrinsic-test/missing_aarch64.txt
+elif [ "${TARGET}" = "armv7-unknown-linux-gnueabihf" ]; then
+    export CPPFLAGS="-fuse-ld=lld -I/usr/arm-linux-gnueabihf/include/ -I/usr/arm-linux-gnueabihf/include/c++/9/arm-linux-gnueabihf/"
+    RUST_LOG=warn cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- crates/intrinsic-test/acle/tools/intrinsic_db/advsimd.csv --runner "${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}" --cppcompiler "clang++-13" --skip crates/intrinsic-test/missing_arm.txt --a32
 fi
 
 if [ "$NORUN" != "1" ] && [ "$NOSTD" != 1 ]; then

crates/intrinsic-test/missing.txt renamed to crates/intrinsic-test/missing_aarch64.txt

@@ -80,3 +80,17 @@ vsm3tt2bq_u32
 vsm4ekeyq_u32
 vsm4eq_u32
 vusmmlaq_s32
+
+# LLVM select error in debug builds
+vqshlu_n_s16
+vqshlu_n_s32
+vqshlu_n_s64
+vqshlu_n_s8
+vqshlub_n_s8
+vqshlud_n_s64
+vqshluh_n_s16
+vqshluq_n_s16
+vqshluq_n_s32
+vqshluq_n_s64
+vqshluq_n_s8
+vqshlus_n_s32

crates/intrinsic-test/missing_arm.txt

@@ -0,0 +1,302 @@
+# Not implemented in stdarch yet
+vbfdot_f32
+vbfdot_lane_f32
+vbfdot_laneq_f32
+vbfdotq_f32
+vbfdotq_lane_f32
+vbfdotq_laneq_f32
+vbfmlalbq_f32
+vbfmlalbq_lane_f32
+vbfmlalbq_laneq_f32
+vbfmlaltq_f32
+vbfmlaltq_lane_f32
+vbfmlaltq_laneq_f32
+vbfmmlaq_f32
+vcmla_f64
+vcmla_lane_f64
+vcmla_laneq_f64
+vcmlaq_lane_f64
+vcmlaq_laneq_f64
+vcmlaq_rot180_lane_f64
+vcmlaq_rot180_laneq_f64
+vcmlaq_rot270_lane_f64
+vcmlaq_rot270_laneq_f64
+vcmlaq_rot90_lane_f64
+vcmlaq_rot90_laneq_f64
+vcmla_rot180_f64
+vcmla_rot180_lane_f64
+vcmla_rot180_laneq_f64
+vcmla_rot270_f64
+vcmla_rot270_lane_f64
+vcmla_rot270_laneq_f64
+vcmla_rot90_f64
+vcmla_rot90_lane_f64
+vcmla_rot90_laneq_f64
+vsudot_laneq_s32
+vsudot_lane_s32
+vsudotq_laneq_s32
+vsudotq_lane_s32
+vusdot_laneq_s32
+vusdot_lane_s32
+vusdotq_laneq_s32
+vusdotq_lane_s32
+vusdotq_s32
+vusdot_s32
+
+# Missing from both Clang and stdarch
+vrnd32x_f64
+vrnd32xq_f64
+vrnd32z_f64
+vrnd32zq_f64
+vrnd64x_f64
+vrnd64xq_f64
+vrnd64z_f64
+vrnd64zq_f64
+
+# Takes too long to compile tests
+vcopyq_laneq_u8
+vcopyq_laneq_s8
+vcopyq_laneq_p8
+vcopyq_lane_u8
+vcopyq_lane_s8
+vcopyq_lane_p8
+vcopy_laneq_u8
+vcopy_laneq_s8
+vcopy_laneq_p8
+vcopy_lane_u8
+vcopy_lane_s8
+vcopy_lane_p8
+
+# QEMU 6.0 doesn't support these instructions
+vmmlaq_s32
+vmmlaq_u32
+vsm3partw1q_u32
+vsm3partw2q_u32
+vsm3ss1q_u32
+vsm3tt1aq_u32
+vsm3tt1bq_u32
+vsm3tt2aq_u32
+vsm3tt2bq_u32
+vsm4ekeyq_u32
+vsm4eq_u32
+vusmmlaq_s32
+
+# Incorrectly marked as supported on A32 in CSV
+vrndn_f64
+vrndnq_f64
+vreinterpretq_f64_u64
+__crc32d
+__crc32cd
+
+# Appears in the Clang header but not implemented in the LLVM ARM backend
+vcmla_f32
+vcmla_lane_f32
+vcmla_laneq_f32
+vcmla_rot180_f32
+vcmla_rot180_lane_f32
+vcmla_rot180_laneq_f32
+vcmla_rot270_f32
+vcmla_rot270_lane_f32
+vcmla_rot270_laneq_f32
+vcmla_rot90_f32
+vcmla_rot90_lane_f32
+vcmla_rot90_laneq_f32
+vcmlaq_f32
+vcmlaq_lane_f32
+vcmlaq_laneq_f32
+vcmlaq_rot180_f32
+vcmlaq_rot180_lane_f32
+vcmlaq_rot180_laneq_f32
+vcmlaq_rot270_f32
+vcmlaq_rot270_lane_f32
+vcmlaq_rot270_laneq_f32
+vcmlaq_rot90_f32
+vcmlaq_rot90_lane_f32
+vcmlaq_rot90_laneq_f32
+
+# CSV claims that it is supported on A32 but Clang has them as A64-only
+vaddq_p64
+vbsl_p64
+vbslq_p64
+vceq_p64
+vceqq_p64
+vceqz_p64
+vceqzq_p64
+vcombine_p64
+vcopy_lane_p64
+vcopy_laneq_p64
+vcopyq_lane_p64
+vcopyq_laneq_p64
+vcreate_p64
+vdup_lane_p64
+vdup_n_p64
+vdupq_lane_p64
+vdupq_n_p64
+vext_p64
+vextq_p64
+vget_high_p64
+vget_lane_p64
+vget_low_p64
+vgetq_lane_p64
+vmovn_high_s16
+vmovn_high_s32
+vmovn_high_s64
+vmovn_high_u16
+vmovn_high_u32
+vmovn_high_u64
+vmull_high_p64
+vmull_p64
+vreinterpret_p16_p64
+vreinterpret_p64_f32
+vreinterpret_p64_p16
+vreinterpret_p64_p8
+vreinterpret_p64_s16
+vreinterpret_p64_s32
+vreinterpret_p64_s8
+vreinterpret_p64_u16
+vreinterpret_p64_u32
+vreinterpret_p64_u64
+vreinterpret_p64_u8
+vreinterpret_p8_p64
+vreinterpretq_p128_f32
+vreinterpretq_p128_p16
+vreinterpretq_p128_p8
+vreinterpretq_p128_s16
+vreinterpretq_p128_s32
+vreinterpretq_p128_s64
+vreinterpretq_p128_s8
+vreinterpretq_p128_u16
+vreinterpretq_p128_u32
+vreinterpretq_p128_u64
+vreinterpretq_p128_u8
+vreinterpretq_p16_p64
+vreinterpretq_p64_f32
+vreinterpretq_p64_p16
+vreinterpretq_p64_p8
+vreinterpretq_p64_s16
+vreinterpretq_p64_s32
+vreinterpretq_p64_s64
+vreinterpretq_p64_s8
+vreinterpretq_p64_u16
+vreinterpretq_p64_u32
+vreinterpretq_p64_u64
+vreinterpretq_p64_u8
+vreinterpretq_p8_p64
+vreinterpretq_s16_p64
+vreinterpretq_s32_p64
+vreinterpretq_s64_p64
+vreinterpretq_s8_p64
+vreinterpretq_u16_p64
+vreinterpretq_u32_p64
+vreinterpretq_u64_p64
+vreinterpretq_u8_p64
+vreinterpret_s16_p64
+vreinterpret_s32_p64
+vreinterpret_s64_p64
+vreinterpret_s8_p64
+vreinterpret_u16_p64
+vreinterpret_u32_p64
+vreinterpret_u64_p64
+vreinterpret_u8_p64
+vset_lane_p64
+vsetq_lane_p64
+vsli_n_p64
+vsliq_n_p64
+vsri_n_p64
+vsriq_n_p64
+vtst_p64
+vtstq_p64
+
+# Implemented in stdarch for AArch64 but missing on ARM
+vadd_s64
+vadd_u64
+vcaddq_rot270_f32
+vcaddq_rot90_f32
+vcadd_rot270_f32
+vcadd_rot90_f32
+vcombine_f32
+vcombine_p16
+vcombine_p8
+vcombine_s16
+vcombine_s32
+vcombine_s64
+vcombine_s8
+vcombine_u16
+vcombine_u32
+vcombine_u64
+vcombine_u8
+vcvtaq_s32_f32
+vcvtaq_u32_f32
+vcvta_s32_f32
+vcvta_u32_f32
+vcvtmq_s32_f32
+vcvtmq_u32_f32
+vcvtm_s32_f32
+vcvtm_u32_f32
+vcvtnq_s32_f32
+vcvtnq_u32_f32
+vcvtn_s32_f32
+vcvtn_u32_f32
+vcvtpq_s32_f32
+vcvtpq_u32_f32
+vcvtp_s32_f32
+vcvtp_u32_f32
+vdot_lane_s32
+vdot_lane_u32
+vdotq_lane_s32
+vdotq_lane_u32
+vdotq_s32
+vdotq_u32
+vdot_s32
+vdot_u32
+vqdmulh_lane_s16
+vqdmulh_lane_s32
+vqdmulhq_lane_s16
+vqdmulhq_lane_s32
+vrnda_f32
+vrnda_f32
+vrndaq_f32
+vrndaq_f32
+vrnd_f32
+vrnd_f32
+vrndi_f32
+vrndi_f32
+vrndiq_f32
+vrndiq_f32
+vrndm_f32
+vrndm_f32
+vrndmq_f32
+vrndmq_f32
+vrndns_f32
+vrndp_f32
+vrndpq_f32
+vrndq_f32
+vrndq_f32
+vrndx_f32
+vrndxq_f32
+
+# LLVM select error in debug builds
+vqrshrn_n_s16
+vqrshrn_n_s32
+vqrshrn_n_s64
+vqrshrn_n_u16
+vqrshrn_n_u32
+vqrshrn_n_u64
+vqrshrun_n_s16
+vqrshrun_n_s32
+vqrshrun_n_s64
+vqshrn_n_s16
+vqshrn_n_s32
+vqshrn_n_s64
+vqshrn_n_u16
+vqshrn_n_u32
+vqshrn_n_u64
+vqshrun_n_s16
+vqshrun_n_s32
+vqshrun_n_s64
+vrshrn_n_s16
+vrshrn_n_s32
+vrshrn_n_s64
+vrshrn_n_u16
+vrshrn_n_u32
+vrshrn_n_u64

crates/intrinsic-test/src/acle_csv_parser.rs

@@ -82,11 +82,17 @@ impl Into<Intrinsic> for ACLEIntrinsicLine {
             })
             .collect();
         let arguments = ArgumentList { args };
+        let a64_only = match &*self.supported_architectures {
+            "A64" => true,
+            "v7/A32/A64" | "A32/A64" => false,
+            _ => panic!("Invalid supported architectures"),
+        };
 
         Intrinsic {
             name: name.to_string(),
             arguments,
             results,
+            a64_only,
         }
     }
 }

crates/intrinsic-test/src/intrinsic.rs

@@ -13,6 +13,9 @@ pub struct Intrinsic {
 
     /// The return type of this intrinsic.
     pub results: IntrinsicType,
+
+    /// Whether this intrinsic is only available on A64.
+    pub a64_only: bool,
 }
 
 impl Intrinsic {