Merge branch 'master' into next

Author: josephlr

.github/workflows/release.yml

@@ -0,0 +1,27 @@
+name: Release
+
+on:
+  push:
+    branches:
+      - 'master'
+
+jobs:
+  release:
+    name: "Release"
+    runs-on: ubuntu-latest
+    timeout-minutes: 15
+    environment: crates_io_release
+
+    steps:
+      - name: "Checkout Repository"
+        uses: actions/checkout@v1
+
+      - name: "Install Python Libraries"
+        run: python -m pip install --user -r requirements.txt
+        working-directory: "scripts"
+
+      - name: "Run release script"
+        run: "python3 scripts/ci-release.py"
+        env:
+          CARGO_REGISTRY_TOKEN: ${{ secrets.CARGO_REGISTRY_TOKEN }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

Cargo.toml

@@ -22,7 +22,7 @@ license = "MIT/Apache-2.0"
 name = "x86_64"
 readme = "README.md"
 repository = "https://github.com/rust-osdev/x86_64"
-version = "0.14.3"
+version = "0.14.4"
 edition = "2018"
 
 [dependencies]

Changelog.md

@@ -1,5 +1,36 @@
 # Unreleased
 
+# 0.14.4 – 2021-07-19
+
+- Add `instructions::tables::sgdt` ([#279](https://github.com/rust-osdev/x86_64/pull/279))
+- Improve control register bits ([#273](https://github.com/rust-osdev/x86_64/pull/273))
+  - Add `Cr0` bits: `EXTENSION_TYPE` (ET)
+  - Add `Cr4` bits:
+    - `KEY_LOCKER` (KL)
+    - `CONTROL_FLOW_ENFORCEMENT` (CET)
+    - `PROTECTION_KEY_SUPERVISOR` (PKS)
+  - Add `XCr0` bits: `BNDREG`, `BNDCSR`, `OPMASK`, `ZMM_HI256`, `HI16_ZMM`
+  - Add consistency checks for `XCr0` bits
+- Add `SelectorErrorCode` for parsing interrupt error codes from `#TS`, `#NP`, `#SS`, and `#GP` ([#274](https://github.com/rust-osdev/x86_64/pull/274))
+- Make `addr::{align_up,  align_down}` const ([#270](https://github.com/rust-osdev/x86_64/pull/270))
+- Make `structures::idt` available on stable Rust ([#271](https://github.com/rust-osdev/x86_64/pull/271))
+  - Use dummy types for the `HandlerFunc`s if the `"abi_x86_interrupt"` feature is disabled
+  - Add unsafe `set_handler_addr` that just takes a `VirtAddr`
+- Add common abstractions for x86 Segments ([#258](https://github.com/rust-osdev/x86_64/pull/258))
+  - Add `SS`, `CS`, `DS`, `ES`, `FS`, `GS` marker types
+  - Add `Segment` trait for reading/writing the segment register
+  - Add `Segment64` trait for reading/writing the segment base
+  - Add `GS::swap()`
+  - Deprecate the corresponding free functions:
+    - `cs`, `set_cs`
+    - `swap_gs`
+    - `load_{ss,ds,es,fs,gs}`
+    - `{wr,rd}{fs,gs}base`
+- Bug fixes:
+  - Corrected documentation typo ([#278](https://github.com/rust-osdev/x86_64/pull/278))
+  - Avoided off-by-one error in `GlobalDescriptorTable::from_raw_slice` when `"const_fn"` is not enabled ([#269](https://github.com/rust-osdev/x86_64/pull/269))
+  - Specify `sysv64` as the calling convention for the `"external_asm"` functions ([#267](https://github.com/rust-osdev/x86_64/pull/267))
+
 # 0.14.3 – 2021-05-14
 
 - Make the following types aliases of the new `PortGeneric` type ([#248](https://github.com/rust-osdev/x86_64/pull/248)):

scripts/ci-release.py

@@ -0,0 +1,36 @@
+import toml
+import requests
+import subprocess
+
+cargo_toml = toml.load("Cargo.toml")
+crate_version = cargo_toml["package"]["version"]
+print("Detected crate version " + crate_version)
+
+api_url = "https://crates.io/api/v1/crates/x86_64/" + crate_version
+released_version = requests.get(api_url).json()
+
+if "version" in released_version:
+    version = released_version["version"]
+    assert (version["crate"] == "x86_64")
+    assert (version["num"] == crate_version)
+    print("Version " + crate_version + " already exists on crates.io")
+
+else:
+    print("Could not find version " + crate_version +
+          " on crates.io; creating a new release")
+
+    print("  Running `cargo publish`")
+    subprocess.run(["cargo", "publish"], check=True)
+
+    tag_name = "v" + crate_version
+    print("  Tagging commit as " + tag_name)
+    sha = subprocess.run(["git", "rev-parse", "HEAD"], check=True,
+                         stdout=subprocess.PIPE).stdout.decode("utf-8").strip()
+    subprocess.run([
+        "gh", "api", "/repos/rust-osdev/x86_64/git/refs",
+        "-X", "POST", "-H", "Accept: application/vnd.github.v3+json",
+        "-F", "ref=refs/tags/" + tag_name,
+        "-F", "sha="+sha
+    ])
+
+    print("  Done")

scripts/requirements.txt

@@ -0,0 +1 @@
+toml

src/instructions/segmentation.rs

@@ -131,9 +131,14 @@ pub struct CS;
 impl Segment for CS {
     get_reg_impl!("cs", x86_64_asm_get_cs);
 
-    /// Note this is special since we cannot directly move to [`CS`]. Instead we
-    /// push the new segment selector and return value on the stack and use
-    /// `retfq` to reload [`CS`] and continue at the end of our function.
+    /// Note this is special since we cannot directly move to [`CS`]; x86 requires the instruction
+    /// pointer and [`CS`] to be set at the same time. To do this, we push the new segment selector
+    /// and return value onto the stack and use a "far return" (`retfq`) to reload [`CS`] and
+    /// continue at the end of our function.
+    ///
+    /// Note we cannot use a "far call" (`lcall`) or "far jmp" (`ljmp`) to do this because then we
+    /// would only be able to jump to 32-bit instruction pointers. Only Intel implements support
+    /// for 64-bit far calls/jumps in long-mode, AMD does not.
     unsafe fn set_reg(sel: SegmentSelector) {
         #[cfg(feature = "inline_asm")]
         asm!(