Merge pull request #338 from rust-osdev/next-with-master

Merge latest changes from `master` into `next` and migrate code

Author: phil-opp

.github/workflows/build.yml

@@ -50,21 +50,29 @@ jobs:
         rustc -Vv
         cargo -Vv
 
-    - name: Cache binaries
-      id: cache-bin
-      uses: actions/cache@v1
-      with:
-        path: binaries
-        key: ${{ runner.OS }}-binaries
-    - name: Add binaries/bin to PATH
-      run: echo "$GITHUB_WORKSPACE/binaries/bin" >> $GITHUB_PATH
-      shell: bash
-
     - name: "Run cargo build"
       uses: actions-rs/cargo@v1
       with:
         command: build
 
+    - name: "Run cargo doc"
+      uses: actions-rs/cargo@v1
+      with:
+        command: doc
+
+    - name: "Run cargo doc for stable"
+      uses: actions-rs/cargo@v1
+      with:
+        command: doc
+        args: --no-default-features --features external_asm,instructions
+      if: runner.os != 'Windows'
+
+    - name: "Run cargo doc without default features"
+      uses: actions-rs/cargo@v1
+      with:
+        command: doc
+        args: --no-default-features
+
     - name: "Run cargo build for stable without instructions"
       uses: actions-rs/cargo@v1
       with:
@@ -113,6 +121,35 @@ jobs:
         cargo build --target i686-unknown-linux-gnu --no-default-features --features nightly
         cargo build --target thumbv7em-none-eabihf --no-default-features --features nightly
 
+  bootloader-test:
+    name: "Bootloader Integration Test"
+
+    strategy:
+      fail-fast: false
+      matrix:
+        platform: [
+          ubuntu-latest,
+          macos-latest,
+          windows-latest
+        ]
+
+    runs-on: ${{ matrix.platform }}
+    timeout-minutes: 15
+
+    steps:
+    - name: "Checkout Repository"
+      uses: actions/checkout@v1
+
+    - name: Cache binaries
+      id: cache-bin
+      uses: actions/cache@v1
+      with:
+        path: binaries
+        key: ${{ runner.OS }}-binaries
+    - name: Add binaries/bin to PATH
+      run: echo "$GITHUB_WORKSPACE/binaries/bin" >> $GITHUB_PATH
+      shell: bash
+
     - name: "Install Rustup Components"
       run: rustup component add rust-src llvm-tools-preview
     - name: "Install cargo-xbuild"
@@ -133,14 +170,10 @@ jobs:
         HOMEBREW_NO_AUTO_UPDATE: 1
         HOMEBREW_NO_BOTTLE_SOURCE_FALLBACK: 1
         HOMEBREW_NO_INSTALL_CLEANUP: 1
-    - name: Install Scoop (Windows)
-      run: |
-        Invoke-Expression (New-Object System.Net.WebClient).DownloadString('https://get.scoop.sh')
-        echo "$HOME\scoop\shims" | Out-File -FilePath $env:GITHUB_PATH -Encoding utf8 -Append
-      if: runner.os == 'Windows'
-      shell: pwsh
     - name: Install QEMU (Windows)
-      run: scoop install qemu
+      run: |
+        choco install qemu --version 2021.5.5
+        echo "$Env:Programfiles\qemu" | Out-File -FilePath $env:GITHUB_PATH -Encoding utf8 -Append
       if: runner.os == 'Windows'
       shell: pwsh
 

Cargo.toml

@@ -22,11 +22,11 @@ license = "MIT/Apache-2.0"
 name = "x86_64"
 readme = "README.md"
 repository = "https://github.com/rust-osdev/x86_64"
-version = "0.14.4"
+version = "0.14.7"
 edition = "2018"
 
 [dependencies]
-bit_field = "0.9.0"
+bit_field = "0.10.1"
 bitflags = "1.3.2"
 volatile = "0.4.4"
 
@@ -37,13 +37,11 @@ cc = { version = "1.0.37", optional = true }
 default = [ "nightly", "instructions" ]
 instructions = []
 external_asm = [ "cc" ]
-nightly = [ "inline_asm", "const_fn", "abi_x86_interrupt" ]
+nightly = [ "inline_asm", "const_fn", "abi_x86_interrupt", "doc_cfg" ]
 inline_asm = []
 abi_x86_interrupt = []
 const_fn = []
-
-[package.metadata.docs.rs]
-rustdoc-args = ["--cfg", "docsrs"]
+doc_cfg = []
 
 [package.metadata.release]
 no-dev-version = true

Changelog.md

@@ -1,5 +1,38 @@
 # Unreleased
 
+# 0.14.7 – 2021-12-18
+
+- fix: build error on the latest nightly ([#329](https://github.com/rust-osdev/x86_64/pull/329))
+- add `set_general_handler` macro ([#285](https://github.com/rust-osdev/x86_64/pull/285))
+- Derive common traits for number, range and enum types ([#315](https://github.com/rust-osdev/x86_64/pull/315))
+- Add the VMM Communication Exception (`#VC`) to the `InterruptDescriptorTable` ([#313](https://github.com/rust-osdev/x86_64/pull/313))
+- fix: enable manipulation of `InterruptStackFrame` ([#312](https://github.com/rust-osdev/x86_64/pull/312))
+- fix docs for `page_table_index` ([#318](https://github.com/rust-osdev/x86_64/pull/318))
+- Remove redundant alignment check ([#314](https://github.com/rust-osdev/x86_64/pull/314))
+- fix(idt): fix panic messages for `index` and `#VC` ([#321](https://github.com/rust-osdev/x86_64/pull/321))
+- remove `const_assert!` in favor of std's `assert!` ([#326](https://github.com/rust-osdev/x86_64/pull/326))
+- Move bootloader integration test to separate CI job ([#330](https://github.com/rust-osdev/x86_64/pull/330))
+
+# 0.14.6 – 2021-09-20
+
+- New `registers::segmentation` module ([#309](https://github.com/rust-osdev/x86_64/pull/309)), containing:
+  - `instructions::segmentation::{Segment, Segment64, CS, DS, ES, FS, GS, SS}`
+  - `structures::gdt::SegmentSelector`
+  - Old locations still re-export all the types, so this is not a breaking change.
+- Fixes build so that `cargo doc --no-default-features` succeeds.
+
+# 0.14.5 – 2021-09-04
+
+- Add `ExceptionVector` enum and additional flags to `PageFaultErrorCode` ([#303](https://github.com/rust-osdev/x86_64/pull/303))
+- Add `clean_up` and `clean_up_with_filter` methods to deallocate unused page tables ([#264](https://github.com/rust-osdev/x86_64/pull/264))
+- Rename some XCr0 and CR4 flags (#[275](https://github.com/rust-osdev/x86_64/pull/275))
+- Expose `MapperFlush::new` and `MapperFlushAll::new` constructor functions ([#296](https://github.com/rust-osdev/x86_64/pull/296))
+- Use `#[cfg(doc)]` instead of docs.rs-specific cfg flag (#[287](https://github.com/rust-osdev/x86_64/pull/287))
+- Some documentation updates:
+  - Update segment register references in `GDT::load*` method to non-deprecated methods ([#301](https://github.com/rust-osdev/x86_64/pull/301))
+  - Remove a panic note ([#300](https://github.com/rust-osdev/x86_64/pull/300))
+- Update `bit_field` dependency ([#306](https://github.com/rust-osdev/x86_64/pull/306))
+
 # 0.14.4 – 2021-07-19
 
 - Add `instructions::tables::sgdt` ([#279](https://github.com/rust-osdev/x86_64/pull/279))

src/addr.rs

@@ -3,6 +3,7 @@
 use core::fmt;
 use core::ops::{Add, AddAssign, Sub, SubAssign};
 
+use crate::structures::paging::page_table::PageTableLevel;
 use crate::structures::paging::{PageOffset, PageTableIndex};
 use bit_field::BitField;
 
@@ -16,7 +17,7 @@ use bit_field::BitField;
 /// On `x86_64`, only the 48 lower bits of a virtual address can be used. The top 16 bits need
 /// to be copies of bit 47, i.e. the most significant bit. Addresses that fulfil this criterium
 /// are called “canonical”. This type guarantees that it always represents a canonical address.
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
 #[repr(transparent)]
 pub struct VirtAddr(u64);
 
@@ -29,7 +30,7 @@ pub struct VirtAddr(u64);
 ///
 /// On `x86_64`, only the 52 lower bits of a physical address can be used. The top 12 bits need
 /// to be zero. This type guarantees that it always represents a valid physical address.
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
 #[repr(transparent)]
 pub struct PhysAddr(u64);
 
@@ -198,6 +199,12 @@ impl VirtAddr {
     pub const fn p4_index(self) -> PageTableIndex {
         PageTableIndex::new_truncate((self.0 >> 12 >> 9 >> 9 >> 9) as u16)
     }
+
+    /// Returns the 9-bit level page table index.
+    #[inline]
+    pub const fn page_table_index(self, level: PageTableLevel) -> PageTableIndex {
+        PageTableIndex::new_truncate((self.0 >> 12 >> ((level as u8 - 1) * 9)) as u16)
+    }
 }
 
 impl fmt::Debug for VirtAddr {
@@ -537,7 +544,7 @@ impl Sub<PhysAddr> for PhysAddr {
 /// feature, the panic message will be "index out of bounds".
 #[inline]
 pub const fn align_down(addr: u64, align: u64) -> u64 {
-    const_assert!(align.is_power_of_two(), "`align` must be a power of two");
+    assert!(align.is_power_of_two(), "`align` must be a power of two");
     addr & !(align - 1)
 }
 
@@ -549,7 +556,7 @@ pub const fn align_down(addr: u64, align: u64) -> u64 {
 /// feature, the panic message will be "index out of bounds".
 #[inline]
 pub const fn align_up(addr: u64, align: u64) -> u64 {
-    const_assert!(align.is_power_of_two(), "`align` must be a power of two");
+    assert!(align.is_power_of_two(), "`align` must be a power of two");
     let align_mask = align - 1;
     if addr & align_mask == 0 {
         addr // already aligned

src/asm/asm.s

@@ -334,3 +334,19 @@ _x86_64_asm_xsetbv:
     movl  %esi, %eax    # Second param is the low 32-bits
     xsetbv              # Third param (high 32-bits) is already in %edx
     retq
+
+.global _x86_64_asm_write_mxcsr
+.p2align 4
+_x86_64_asm_write_mxcsr:
+    pushq %rdi
+    ldmxcsr (%rsp)
+    popq %rdi
+    retq
+
+.global _x86_64_asm_read_mxcsr
+.p2align 4
+_x86_64_asm_read_mxcsr:
+    pushq $0
+    stmxcsr (%rsp)
+    popq %rax
+    retq

src/asm/mod.rs

@@ -299,4 +299,16 @@ extern "sysv64" {
         link_name = "_x86_64_asm_xsetbv"
     )]
     pub(crate) fn x86_64_asm_xsetbv(xcr: u32, low: u32, high: u32);
+
+    #[cfg_attr(
+        any(target_env = "gnu", target_env = "musl"),
+        link_name = "_x86_64_asm_read_mxcsr"
+    )]
+    pub(crate) fn x86_64_asm_read_mxcsr() -> u32;
+
+    #[cfg_attr(
+        any(target_env = "gnu", target_env = "musl"),
+        link_name = "_x86_64_asm_write_mxcsr"
+    )]
+    pub(crate) fn x86_64_asm_write_mxcsr(val: u32);
 }

src/instructions/interrupts.rs

@@ -1,5 +1,8 @@
 //! Enabling and disabling interrupts
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Returns whether interrupts are enabled.
 #[inline]
 pub fn are_enabled() -> bool {
@@ -156,7 +159,12 @@ pub fn int3() {
 /// It can also cause memory/register corruption depending on the interrupt
 /// implementation (if it expects values/pointers to be passed in registers).
 #[cfg(feature = "inline_asm")]
-#[cfg_attr(docsrs, doc(cfg(any(feature = "nightly", feature = "inline_asm"))))]
+#[cfg_attr(
+    feature = "doc_cfg",
+    doc(cfg(any(feature = "nightly", feature = "inline_asm")))
+)]
 pub unsafe fn software_interrupt<const NUM: u8>() {
-    asm!("int {num}", num = const NUM, options(nomem, nostack));
+    unsafe {
+        asm!("int {num}", num = const NUM, options(nomem, nostack));
+    }
 }

src/instructions/mod.rs

@@ -9,6 +9,9 @@ pub mod segmentation;
 pub mod tables;
 pub mod tlb;
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Halts the CPU until the next interrupt arrives.
 #[inline]
 pub fn hlt() {
@@ -54,7 +57,10 @@ pub fn bochs_breakpoint() {
 /// Gets the current instruction pointer. Note that this is only approximate as it requires a few
 /// instructions to execute.
 #[cfg(feature = "inline_asm")]
-#[cfg_attr(docsrs, doc(cfg(any(feature = "nightly", feature = "inline_asm"))))]
+#[cfg_attr(
+    feature = "doc_cfg",
+    doc(cfg(any(feature = "nightly", feature = "inline_asm")))
+)]
 #[inline(always)]
 pub fn read_rip() -> crate::VirtAddr {
     let rip: u64;