registers: add extra flags for CR0, CR4, and XCR0

Alos, add extra checks when writing to XCR0.

Signed-off-by: Ethin Probst <[email protected]>
Signed-off-by: Joe Richey <[email protected]>

Author: ethindp

src/registers/control.rs

@@ -24,6 +24,8 @@ bitflags! {
         ///
         /// This flags allows lazily saving x87/MMX/SSE instructions on hardware context switches.
         const TASK_SWITCHED = 1 << 3;
+        /// Indicates support of 387DX math coprocessor instructions when set
+        const EXTENSION_TYPE = 1 << 4;
         /// Enables the native error reporting mechanism for x87 FPU errors.
         const NUMERIC_ERROR = 1 << 5;
         /// Controls whether supervisor-level writes to read-only pages are inhibited.
@@ -114,14 +116,20 @@ bitflags! {
         const PCID = 1 << 17;
         /// Enables extendet processor state management instructions, including XGETBV and XSAVE.
         const OSXSAVE = 1 << 18;
+        /// When set, the `LOADIWKEY` instruction is available; additionally, if system firmware has activated the AES key locker instructions, register EBX of CPUID leaf 0x19, bit 0 (AESKLE) is set and the AES key locker instructions are enabled. See the [Intel Key Locker Specification](https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html) for information on this feature.
+        const KEY_LOCKER = 1 << 19;
         /// Prevents the execution of instructions that reside in pages accessible by user-mode
         /// software when the processor is in supervisor-mode.
         const SUPERVISOR_MODE_EXECUTION_PROTECTION = 1 << 20;
         /// Enables restrictions for supervisor-mode software when reading data from user-mode
         /// pages.
         const SUPERVISOR_MODE_ACCESS_PREVENTION = 1 << 21;
-        /// Enables 4-level paging to associate each linear address with a protection key.
+        /// Enables 4-level and 5-level paging to associate each linear address with a protection key in user mode.
         const PROTECTION_KEY = 1 << 22;
+        /// When set, enables intel control-flow enforcement technology. See chapter 18 of the Intel software developer manuals, volume 1, for more information.
+        const CONTROL_FLOW_ENFORCEMENT = 1 << 23;
+        /// When set, allows 4-level and 5-level paging implementations to use the `IA32_PKRS` MSR to specify, for each protection key, whether supervisor-mode linear addresses with a particular protection key can be read or written.
+        const PROTECTION_KEY_SUPERVISOR = 1 << 24;
     }
 }
 

src/registers/xcontrol.rs

@@ -16,8 +16,18 @@ bitflags! {
         /// Enables 256-bit SSE
         /// Must be set to enable AVX
         const YMM = 1<<2;
+        /// When set, MPX instructions are enabled and the bound registers BND0-BND3 can be managed by XSAVE.
+        const BNDREG = 1 << 3;
+        /// When set, MPX instructions can be executed and XSAVE can manage the BNDCFGU and BNDSTATUS registers.
+        const BNDCSR = 1 << 4;
+        /// If set, AVX-512 instructions can be executed and XSAVE can manage the K0-K7 mask registers.
+        const OPMASK = 1 << 5;
+        /// If set, AVX-512 instructions can be executed and XSAVE can be used to manage the upper halves of the lower ZMM registers.
+        const ZMM_HI256 = 1 << 6;
+        /// If set, AVX-512 instructions can be executed and XSAVE can manage the upper ZMM registers.
+        const HI16_ZMM = 1 << 7;
         /// When set, PKRU state management is supported by
-        /// ZSAVE/XRSTOR
+        /// XSAVE/XRSTOR
         const MPK = 1<<9;
         /// When set the Lightweight Profiling extensions are enabled
         const LWP = 1<<62;
@@ -68,6 +78,13 @@ mod x86_64 {
             let old_value = Self::read_raw();
             let reserved = old_value & !(XCr0Flags::all().bits());
             let new_value = reserved | flags.bits();
+            assert!(flags.contains(XCr0Flags::X87), "The X87 flag must be set");
+            assert!((flags.contains(XCr0Flags::AVX) && flags.contains(XCr0Flags::OPMASK) && flags.contains(XCr0Flags::ZMM_HI256) && flags.contains(XCr0Flags::HI16_ZMM)) || !(flags.contains(XCr0Flags::AVX) && flags.contains(XCr0Flags::OPMASK) && flags.contains(XCr0Flags::ZMM_HI256) && flags.contains(XCr0Flags::HI16_ZMM)), "You must enable AVX to set or unset any of XCR0.opmask, XCR0.ZMM_Hi256, and XCR0.Hi16_ZMM");
+            if !flags.contains(XCr0Flags::AVX) && (flags.contains(XCr0Flags::OPMASK) || flags.contains(XCr0Flags::ZMM_HI256) || flags.contains(XCr0Flags::HI16_ZMM)) {
+            panic!("You must have AVX enabled to set XCR0.opmask, XCR0.ZMM_Hi256, or XCR0.Hi16_ZMM");
+            }
+            assert!((flags.contains(XCr0Flags::BNDREG) && flags.contains(XCr0Flags::BNDCSR)) || !(flags.contains(XCr0Flags::BNDREG) && flags.contains(XCr0Flags::BNDCSR)), "BNDREG and BNDCSR must be set and unset together");
+            assert!((flags.contains(XCr0Flags::OPMASK) && flags.contains(XCr0Flags::ZMM_HI256) && flags.contains(XCr0Flags::HI16_ZMM)) || !(flags.contains(XCr0Flags::OPMASK) && flags.contains(XCr0Flags::ZMM_HI256) && flags.contains(XCr0Flags::HI16_ZMM)), "You must set or unset all of XCR0.opmask, XCR0.ZMM_Hi256, and XCR0.Hi16_ZMM");
 
             Self::write_raw(new_value);
         }