Add registers::debug

Author: mkroening

src/registers/debug.rs

@@ -0,0 +1,398 @@
+//! Functions to read and write debug registers.
+
+#![allow(missing_docs)] // TODO: Add docs
+#![deny(unsafe_op_in_unsafe_fn)]
+
+use core::convert::TryFrom;
+use core::mem;
+
+use crate::VirtAddr;
+
+use bitflags::bitflags;
+
+pub trait DebugAddressRegister {
+    /// Reads the current breakpoint address.
+    fn read() -> VirtAddr;
+
+    /// Writes the provided breakpoint address.
+    fn write(addr: VirtAddr);
+}
+
+macro_rules! debug_address_register_impl {
+    ($Dr:ident, $dr:literal) => {
+        #[doc = concat!("Debug Address Register (", $dr,") holding the address of a breakpoint.")]
+        #[derive(Debug)]
+        pub struct $Dr;
+
+        impl DebugAddressRegister for $Dr {
+            #[inline]
+            fn read() -> VirtAddr {
+                let addr;
+                unsafe {
+                    asm!(concat!("mov {}, ", $dr), out(reg) addr, options(nostack, preserves_flags));
+                }
+                VirtAddr::new(addr)
+            }
+
+            #[inline]
+            fn write(addr: VirtAddr) {
+                unsafe {
+                    asm!(concat!("mov ", $dr, ", {}"), in(reg) addr.as_u64(), options(nostack, preserves_flags));
+                }
+            }
+        }
+    };
+}
+
+debug_address_register_impl!(Dr0, "DR0");
+debug_address_register_impl!(Dr1, "DR1");
+debug_address_register_impl!(Dr2, "DR2");
+debug_address_register_impl!(Dr3, "DR3");
+
+/// Debug Status Register (DR6).
+///
+/// Reports debug conditions from the last debug exception.
+#[derive(Debug)]
+pub struct Dr6;
+
+bitflags! {
+    /// Debug condition flags of the [`Dr6`] register.
+    pub struct Dr6Flags: u64 {
+        /// Breakpoint condition 0 was detected.
+        const TRAP0 = 1;
+
+        /// Breakpoint condition 1 was detected.
+        const TRAP1 = 1 << 1;
+
+        /// Breakpoint condition 2 was detected.
+        const TRAP2 = 1 << 2;
+
+        /// Breakpoint condition 3 was detected.
+        const TRAP3 = 1 << 3;
+
+        /// Breakpoint condition was detected.
+        const TRAP = Self::TRAP0.bits | Self::TRAP1.bits | Self::TRAP2.bits | Self::TRAP3.bits;
+
+        /// Next instruction accesses one of the debug registers.
+        ///
+        /// Enabled via [`Dr7Flags::GENERAL_DETECT_ENABLE`].
+        const ACCESS_DETECTED = 1 << 13;
+
+        /// CPU is in single-step execution mode.
+        ///
+        /// Enabled via [`RFlags::TRAP_FLAG`].
+        const STEP = 1 << 14;
+
+        /// Task switch.
+        ///
+        /// Enabled via the debug trap flag in the TSS of the target task.
+        const SWITCH = 1 << 15;
+
+        /// When *clear*, indicates a debug or breakpoint exception inside an RTM region.
+        ///
+        /// Enabled via [`Dr7Flags::RESTRICTED_TRANSACTIONAL_MEMORY`] and the
+        /// RTM flag in the `IA32_DEBUGCTL` [`Msr`].
+        const RTM = 1 << 16;
+    }
+}
+
+impl Dr6 {
+    /// Read the current set of DR6 flags.
+    #[inline]
+    pub fn read() -> Dr6Flags {
+        Dr6Flags::from_bits_truncate(Self::read_raw())
+    }
+
+    /// Read the current raw DR6 value.
+    #[inline]
+    pub fn read_raw() -> u64 {
+        let value;
+        unsafe {
+            asm!("mov {}, dr6", out(reg) value, options(nostack, preserves_flags));
+        }
+        value
+    }
+}
+
+bitflags! {
+    #[repr(transparent)]
+    pub struct Dr7Flags: u64 {
+        const LOCAL_BREAKPOINT_0_ENABLE = 1;
+
+        const LOCAL_BREAKPOINT_1_ENABLE = 1 << 2;
+
+        const LOCAL_BREAKPOINT_2_ENABLE = 1 << 4;
+
+        const LOCAL_BREAKPOINT_3_ENABLE = 1 << 6;
+
+        const GLOBAL_BREAKPOINT_0_ENABLE = 1 << 1;
+
+        const GLOBAL_BREAKPOINT_1_ENABLE = 1 << 3;
+
+        const GLOBAL_BREAKPOINT_2_ENABLE = 1 << 5;
+
+        const GLOBAL_BREAKPOINT_3_ENABLE = 1 << 7;
+
+        const LOCAL_EXACT_BREAKPOINT_ENABLE = 1 << 8;
+
+        const GLOBAL_EXACT_BREAKPOINT_ENABLE = 1 << 9;
+
+        const RESTRICTED_TRANSACTIONAL_MEMORY = 1 << 11;
+
+        const GENERAL_DETECT_ENABLE = 1 << 13;
+    }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum HwBreakpointCondition {
+    InstructionExecution = 0b00,
+    DataWrites = 0b01,
+    IoReadsWrites = 0b10,
+    DataReadsWrites = 0b11,
+}
+
+impl HwBreakpointCondition {
+    const fn bit_position(n: u8) -> u8 {
+        16 + 4 * n
+    }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum HwBreakpointSize {
+    Length1B = 0b00,
+    Length2B = 0b01,
+    Length8B = 0b10,
+    Length4B = 0b11,
+}
+
+impl HwBreakpointSize {
+    const fn bit_position(n: u8) -> u8 {
+        18 + 4 * n
+    }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub struct TryFromIntError(());
+
+impl From<core::num::TryFromIntError> for TryFromIntError {
+    fn from(_: core::num::TryFromIntError) -> Self {
+        Self(())
+    }
+}
+
+impl TryFrom<usize> for HwBreakpointSize {
+    type Error = TryFromIntError;
+
+    fn try_from(size: usize) -> Result<Self, Self::Error> {
+        match size {
+            1 => Ok(Self::Length1B),
+            2 => Ok(Self::Length2B),
+            8 => Ok(Self::Length8B),
+            4 => Ok(Self::Length4B),
+            _ => Err(TryFromIntError(())),
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub struct Dr7Value {
+    bits: u64,
+}
+
+impl From<Dr7Flags> for Dr7Value {
+    fn from(dr7_flags: Dr7Flags) -> Self {
+        Self::from_bits_truncate(dr7_flags.bits())
+    }
+}
+
+macro_rules! set_condition_impl {
+    ($f:ident, $n:expr) => {
+        #[inline]
+        pub const fn $f(&mut self, condition: HwBreakpointCondition) {
+            unsafe {
+                self.set_condition($n, condition);
+            }
+        }
+    };
+}
+
+macro_rules! get_condition_impl {
+    ($f:ident, $n:expr) => {
+        #[inline]
+        pub fn $f(&self) -> HwBreakpointCondition {
+            unsafe { self.get_condition($n) }
+        }
+    };
+}
+
+macro_rules! set_size_impl {
+    ($f:ident, $n:expr) => {
+        #[inline]
+        pub const fn $f(&mut self, size: HwBreakpointSize) {
+            unsafe {
+                self.set_size($n, size);
+            }
+        }
+    };
+}
+
+macro_rules! get_size_impl {
+    ($f:ident, $n:expr) => {
+        #[inline]
+        pub fn $f(&self) -> HwBreakpointSize {
+            unsafe { self.get_size($n) }
+        }
+    };
+}
+
+impl Dr7Value {
+    const fn mask() -> u64 {
+        let field_mask = (1 << 32) - (1 << 16);
+        let flag_mask = Dr7Flags::all().bits();
+        field_mask | flag_mask
+    }
+
+    #[inline]
+    pub const fn from_bits(bits: u64) -> Option<Self> {
+        if (bits & Self::mask()) == 0 {
+            Some(Self { bits })
+        } else {
+            None
+        }
+    }
+
+    #[inline]
+    pub const fn from_bits_truncate(bits: u64) -> Self {
+        Self {
+            bits: bits & !Self::mask(),
+        }
+    }
+
+    #[inline]
+    pub const unsafe fn from_bits_unchecked(bits: u64) -> Self {
+        Self { bits }
+    }
+
+    #[inline]
+    pub const fn bits(&self) -> u64 {
+        self.bits
+    }
+
+    #[inline]
+    pub const fn flags(&self) -> Dr7Flags {
+        Dr7Flags::from_bits_truncate(self.bits)
+    }
+
+    #[inline]
+    pub fn flags_mut(&mut self) -> &mut Dr7Flags {
+        // SAFETY: `Dr7Flags` has the same representation as
+        unsafe { mem::transmute(self.bits) }
+    }
+
+    /// # Safety
+    ///
+    /// `n` must be in `0..=3`.
+    const unsafe fn set_condition(&mut self, n: u8, condition: HwBreakpointCondition) {
+        let pos = HwBreakpointCondition::bit_position(n);
+        // Clear value
+        self.bits &= !(0b11 << pos);
+        // Insert value
+        self.bits |= (condition as u64) << pos;
+    }
+
+    set_condition_impl!(set_condition_0, 0);
+    set_condition_impl!(set_condition_1, 1);
+    set_condition_impl!(set_condition_2, 2);
+    set_condition_impl!(set_condition_3, 3);
+
+    /// # Safety
+    ///
+    /// `n` must be in `0..=3`.
+    unsafe fn get_condition(&self, n: u8) -> HwBreakpointCondition {
+        let pos = HwBreakpointCondition::bit_position(n);
+        let condition = (self.bits >> pos) & 0b11;
+        // SAFETY: All two bit patterns are valid variants
+        unsafe { mem::transmute(condition as u8) }
+    }
+
+    get_condition_impl!(get_condition_0, 0);
+    get_condition_impl!(get_condition_1, 1);
+    get_condition_impl!(get_condition_2, 2);
+    get_condition_impl!(get_condition_3, 3);
+
+    /// # Safety
+    ///
+    /// `n` must be in `0..=3`.
+    const unsafe fn set_size(&mut self, n: u8, size: HwBreakpointSize) {
+        let pos = HwBreakpointSize::bit_position(n);
+        // Clear value
+        self.bits &= !(0b11 << pos);
+        // Insert value
+        self.bits |= (size as u64) << pos;
+    }
+
+    set_size_impl!(set_size_0, 0);
+    set_size_impl!(set_size_1, 1);
+    set_size_impl!(set_size_2, 2);
+    set_size_impl!(set_size_3, 3);
+
+    /// # Safety
+    ///
+    /// `n` must be in `0..=3`.
+    unsafe fn get_size(&self, n: u8) -> HwBreakpointSize {
+        let pos = HwBreakpointSize::bit_position(n);
+        let size = (self.bits >> pos) & 0b11;
+        // SAFETY: All two bit patterns are valid variants
+        unsafe { mem::transmute(size as u8) }
+    }
+
+    get_size_impl!(get_size_0, 0);
+    get_size_impl!(get_size_1, 1);
+    get_size_impl!(get_size_2, 2);
+    get_size_impl!(get_size_3, 3);
+}
+
+/// Debug Control Register (DR7).
+///
+/// Configures debug conditions for debug exceptions.
+#[derive(Debug)]
+pub struct Dr7;
+
+impl Dr7 {
+    /// Read the current set of DR6 flags.
+    #[inline]
+    pub fn read() -> Dr7Value {
+        Dr7Value::from_bits_truncate(Self::read_raw())
+    }
+
+    /// Read the current raw DR6 value.
+    #[inline]
+    pub fn read_raw() -> u64 {
+        let value;
+        unsafe {
+            asm!("mov {}, dr7", out(reg) value, options(nostack, preserves_flags));
+        }
+        value
+    }
+
+    /// Write DR7 value.
+    ///
+    /// Preserves the value of reserved fields.
+    #[inline]
+    pub fn write(value: Dr7Value) {
+        let old_value = Self::read_raw();
+        let reserved = old_value & !Dr7Value::mask();
+        let new_value = reserved | value.bits();
+
+        Self::write_raw(new_value)
+    }
+
+    #[inline]
+    pub fn write_raw(value: u64) {
+        unsafe {
+            asm!("mov dr7, {}", in(reg) value, options(nostack, preserves_flags));
+        }
+    }
+}