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[Mips] Guard emission of CFI instructions by MF.needsFrameMoves()
Don't emit CFI instructions when they will be skipped by AsmPrinter. Also, use a helper class to simplify emission. As a side effect, this seems to have unblocked delay slot filler optimization on some tests, though it is not obvious to me whether the transformations are legitimate. Similar to llvm#135845 and llvm#136060.
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7 files changed

+65
-124
lines changed

7 files changed

+65
-124
lines changed

‎llvm/lib/Target/Mips/Mips16FrameLowering.cpp

Lines changed: 8 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "MipsRegisterInfo.h"
1717
#include "MipsSubtarget.h"
1818
#include "llvm/ADT/BitVector.h"
19+
#include "llvm/CodeGen/CFIInstBuilder.h"
1920
#include "llvm/CodeGen/MachineBasicBlock.h"
2021
#include "llvm/CodeGen/MachineFrameInfo.h"
2122
#include "llvm/CodeGen/MachineFunction.h"
@@ -24,9 +25,6 @@
2425
#include "llvm/CodeGen/MachineModuleInfo.h"
2526
#include "llvm/CodeGen/TargetFrameLowering.h"
2627
#include "llvm/IR/DebugLoc.h"
27-
#include "llvm/MC/MCContext.h"
28-
#include "llvm/MC/MCDwarf.h"
29-
#include "llvm/MC/MCRegisterInfo.h"
3028
#include "llvm/Support/MathExtras.h"
3129
#include <cstdint>
3230
#include <vector>
@@ -52,32 +50,17 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
5250
// No need to allocate space on the stack.
5351
if (StackSize == 0 && !MFI.adjustsStack()) return;
5452

55-
const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();
56-
5753
// Adjust stack.
5854
TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
5955

60-
// emit ".cfi_def_cfa_offset StackSize"
61-
unsigned CFIIndex =
62-
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
63-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
64-
.addCFIIndex(CFIIndex);
65-
66-
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
67-
68-
if (!CSI.empty()) {
69-
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
70-
71-
for (const CalleeSavedInfo &I : CSI) {
72-
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
73-
MCRegister Reg = I.getReg();
74-
unsigned DReg = MRI->getDwarfRegNum(Reg, true);
75-
unsigned CFIIndex = MF.addFrameInst(
76-
MCCFIInstruction::createOffset(nullptr, DReg, Offset));
77-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
78-
.addCFIIndex(CFIIndex);
79-
}
56+
if (MF.needsFrameMoves()) {
57+
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::NoFlags);
58+
CFIBuilder.buildDefCFAOffset(StackSize);
59+
60+
for (const CalleeSavedInfo &I : MFI.getCalleeSavedInfo())
61+
CFIBuilder.buildOffset(I.getReg(), MFI.getObjectOffset(I.getFrameIdx()));
8062
}
63+
8164
if (hasFP(MF))
8265
BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
8366
.addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);

‎llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

Lines changed: 28 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "llvm/ADT/BitVector.h"
2020
#include "llvm/ADT/StringRef.h"
2121
#include "llvm/ADT/StringSwitch.h"
22+
#include "llvm/CodeGen/CFIInstBuilder.h"
2223
#include "llvm/CodeGen/MachineBasicBlock.h"
2324
#include "llvm/CodeGen/MachineFrameInfo.h"
2425
#include "llvm/CodeGen/MachineFunction.h"
@@ -33,8 +34,6 @@
3334
#include "llvm/CodeGen/TargetSubtargetInfo.h"
3435
#include "llvm/IR/DebugLoc.h"
3536
#include "llvm/IR/Function.h"
36-
#include "llvm/MC/MCDwarf.h"
37-
#include "llvm/MC/MCRegisterInfo.h"
3837
#include "llvm/Support/CodeGen.h"
3938
#include "llvm/Support/ErrorHandling.h"
4039
#include "llvm/Support/MathExtras.h"
@@ -426,76 +425,54 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
426425
// No need to allocate space on the stack.
427426
if (StackSize == 0 && !MFI.adjustsStack()) return;
428427

429-
const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();
428+
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::NoFlags);
429+
bool NeedsDwarfCFI = MF.needsFrameMoves();
430430

431431
// Adjust stack.
432432
TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
433-
434-
// emit ".cfi_def_cfa_offset StackSize"
435-
unsigned CFIIndex =
436-
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
437-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
438-
.addCFIIndex(CFIIndex);
433+
if (NeedsDwarfCFI)
434+
CFIBuilder.buildDefCFAOffset(StackSize);
439435

440436
if (MF.getFunction().hasFnAttribute("interrupt"))
441437
emitInterruptPrologueStub(MF, MBB);
442438

443439
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
444440

445-
if (!CSI.empty()) {
446-
// Find the instruction past the last instruction that saves a callee-saved
447-
// register to the stack.
448-
for (unsigned i = 0; i < CSI.size(); ++i)
449-
++MBBI;
441+
// Find the instruction past the last instruction that saves a callee-saved
442+
// register to the stack.
443+
std::advance(MBBI, CSI.size());
444+
CFIBuilder.setInsertPoint(MBBI);
450445

451-
// Iterate over list of callee-saved registers and emit .cfi_offset
452-
// directives.
446+
// Iterate over list of callee-saved registers and emit .cfi_offset
447+
// directives.
448+
if (NeedsDwarfCFI) {
453449
for (const CalleeSavedInfo &I : CSI) {
454450
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
455451
MCRegister Reg = I.getReg();
456452

457453
// If Reg is a double precision register, emit two cfa_offsets,
458454
// one for each of the paired single precision registers.
459455
if (Mips::AFGR64RegClass.contains(Reg)) {
460-
unsigned Reg0 =
461-
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
462-
unsigned Reg1 =
463-
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
456+
MCRegister Reg0 = RegInfo.getSubReg(Reg, Mips::sub_lo);
457+
MCRegister Reg1 = RegInfo.getSubReg(Reg, Mips::sub_hi);
464458

465459
if (!STI.isLittle())
466460
std::swap(Reg0, Reg1);
467461

468-
unsigned CFIIndex = MF.addFrameInst(
469-
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
470-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
471-
.addCFIIndex(CFIIndex);
472-
473-
CFIIndex = MF.addFrameInst(
474-
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
475-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
476-
.addCFIIndex(CFIIndex);
462+
CFIBuilder.buildOffset(Reg0, Offset);
463+
CFIBuilder.buildOffset(Reg1, Offset + 4);
477464
} else if (Mips::FGR64RegClass.contains(Reg)) {
478-
unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
479-
unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
465+
MCRegister Reg0 = Reg;
466+
MCRegister Reg1 = Reg + 1;
480467

481468
if (!STI.isLittle())
482469
std::swap(Reg0, Reg1);
483470

484-
unsigned CFIIndex = MF.addFrameInst(
485-
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
486-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
487-
.addCFIIndex(CFIIndex);
488-
489-
CFIIndex = MF.addFrameInst(
490-
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
491-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
492-
.addCFIIndex(CFIIndex);
471+
CFIBuilder.buildOffset(Reg0, Offset);
472+
CFIBuilder.buildOffset(Reg1, Offset + 4);
493473
} else {
494474
// Reg is either in GPR32 or FGR32.
495-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
496-
nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
497-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
498-
.addCFIIndex(CFIIndex);
475+
CFIBuilder.buildOffset(Reg, Offset);
499476
}
500477
}
501478
}
@@ -511,13 +488,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
511488
}
512489

513490
// Emit .cfi_offset directives for eh data registers.
514-
for (int I = 0; I < 4; ++I) {
515-
int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
516-
unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
517-
unsigned CFIIndex = MF.addFrameInst(
518-
MCCFIInstruction::createOffset(nullptr, Reg, Offset));
519-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
520-
.addCFIIndex(CFIIndex);
491+
if (NeedsDwarfCFI) {
492+
for (int I = 0; I < 4; ++I) {
493+
int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
494+
CFIBuilder.buildOffset(ABI.GetEhDataReg(I), Offset);
495+
}
521496
}
522497
}
523498

@@ -527,11 +502,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
527502
BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
528503
.setMIFlag(MachineInstr::FrameSetup);
529504

530-
// emit ".cfi_def_cfa_register $fp"
531-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
532-
nullptr, MRI->getDwarfRegNum(FP, true)));
533-
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
534-
.addCFIIndex(CFIIndex);
505+
if (NeedsDwarfCFI)
506+
CFIBuilder.buildDefCFARegister(FP);
535507

536508
if (RegInfo.hasStackRealignment(MF)) {
537509
// addiu $Reg, $zero, -MaxAlignment

‎llvm/test/CodeGen/Mips/analyzebranch.ll

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ define double @foo(double %a, double %b) nounwind readnone {
132132
; MIPS64R6-NEXT: mfc1 $1, $f1
133133
; MIPS64R6-NEXT: andi $1, $1, 1
134134
; MIPS64R6-NEXT: bnez $1, .LBB0_2
135-
; MIPS64R6-NEXT: mov.d $f0, $f12
135+
; MIPS64R6-NEXT: mov.d $f0, $f12
136136
; MIPS64R6-NEXT: # %bb.1: # %if.else
137137
; MIPS64R6-NEXT: dmtc1 $zero, $f0
138138
; MIPS64R6-NEXT: cmp.ule.d $f1, $f13, $f0
@@ -167,11 +167,10 @@ define void @f1(float %f) nounwind {
167167
; MIPS32-LABEL: f1:
168168
; MIPS32: # %bb.0: # %entry
169169
; MIPS32-NEXT: addiu $sp, $sp, -24
170-
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
171170
; MIPS32-NEXT: mtc1 $zero, $f0
172171
; MIPS32-NEXT: c.eq.s $f12, $f0
173172
; MIPS32-NEXT: bc1f $BB1_2
174-
; MIPS32-NEXT: nop
173+
; MIPS32-NEXT: sw $ra, 20($sp)
175174
; MIPS32-NEXT: # %bb.1: # %if.end
176175
; MIPS32-NEXT: jal f2
177176
; MIPS32-NEXT: nop
@@ -185,11 +184,10 @@ define void @f1(float %f) nounwind {
185184
; MIPS32R2-LABEL: f1:
186185
; MIPS32R2: # %bb.0: # %entry
187186
; MIPS32R2-NEXT: addiu $sp, $sp, -24
188-
; MIPS32R2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
189187
; MIPS32R2-NEXT: mtc1 $zero, $f0
190188
; MIPS32R2-NEXT: c.eq.s $f12, $f0
191189
; MIPS32R2-NEXT: bc1f $BB1_2
192-
; MIPS32R2-NEXT: nop
190+
; MIPS32R2-NEXT: sw $ra, 20($sp)
193191
; MIPS32R2-NEXT: # %bb.1: # %if.end
194192
; MIPS32R2-NEXT: jal f2
195193
; MIPS32R2-NEXT: nop
@@ -203,13 +201,12 @@ define void @f1(float %f) nounwind {
203201
; MIPS32r6-LABEL: f1:
204202
; MIPS32r6: # %bb.0: # %entry
205203
; MIPS32r6-NEXT: addiu $sp, $sp, -24
206-
; MIPS32r6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
207204
; MIPS32r6-NEXT: mtc1 $zero, $f0
208205
; MIPS32r6-NEXT: cmp.eq.s $f0, $f12, $f0
209206
; MIPS32r6-NEXT: mfc1 $1, $f0
210207
; MIPS32r6-NEXT: andi $1, $1, 1
211-
; MIPS32r6-NEXT: beqzc $1, $BB1_2
212-
; MIPS32r6-NEXT: nop
208+
; MIPS32r6-NEXT: beqz $1, $BB1_2
209+
; MIPS32r6-NEXT: sw $ra, 20($sp)
213210
; MIPS32r6-NEXT: # %bb.1: # %if.end
214211
; MIPS32r6-NEXT: jal f2
215212
; MIPS32r6-NEXT: nop
@@ -223,11 +220,10 @@ define void @f1(float %f) nounwind {
223220
; MIPS4-LABEL: f1:
224221
; MIPS4: # %bb.0: # %entry
225222
; MIPS4-NEXT: daddiu $sp, $sp, -16
226-
; MIPS4-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
227223
; MIPS4-NEXT: mtc1 $zero, $f0
228224
; MIPS4-NEXT: c.eq.s $f12, $f0
229225
; MIPS4-NEXT: bc1f .LBB1_2
230-
; MIPS4-NEXT: nop
226+
; MIPS4-NEXT: sd $ra, 8($sp)
231227
; MIPS4-NEXT: # %bb.1: # %if.end
232228
; MIPS4-NEXT: jal f2
233229
; MIPS4-NEXT: nop
@@ -241,11 +237,10 @@ define void @f1(float %f) nounwind {
241237
; MIPS64-LABEL: f1:
242238
; MIPS64: # %bb.0: # %entry
243239
; MIPS64-NEXT: daddiu $sp, $sp, -16
244-
; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
245240
; MIPS64-NEXT: mtc1 $zero, $f0
246241
; MIPS64-NEXT: c.eq.s $f12, $f0
247242
; MIPS64-NEXT: bc1f .LBB1_2
248-
; MIPS64-NEXT: nop
243+
; MIPS64-NEXT: sd $ra, 8($sp)
249244
; MIPS64-NEXT: # %bb.1: # %if.end
250245
; MIPS64-NEXT: jal f2
251246
; MIPS64-NEXT: nop
@@ -259,11 +254,10 @@ define void @f1(float %f) nounwind {
259254
; MIPS64R2-LABEL: f1:
260255
; MIPS64R2: # %bb.0: # %entry
261256
; MIPS64R2-NEXT: daddiu $sp, $sp, -16
262-
; MIPS64R2-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
263257
; MIPS64R2-NEXT: mtc1 $zero, $f0
264258
; MIPS64R2-NEXT: c.eq.s $f12, $f0
265259
; MIPS64R2-NEXT: bc1f .LBB1_2
266-
; MIPS64R2-NEXT: nop
260+
; MIPS64R2-NEXT: sd $ra, 8($sp)
267261
; MIPS64R2-NEXT: # %bb.1: # %if.end
268262
; MIPS64R2-NEXT: jal f2
269263
; MIPS64R2-NEXT: nop
@@ -277,13 +271,12 @@ define void @f1(float %f) nounwind {
277271
; MIPS64R6-LABEL: f1:
278272
; MIPS64R6: # %bb.0: # %entry
279273
; MIPS64R6-NEXT: daddiu $sp, $sp, -16
280-
; MIPS64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
281274
; MIPS64R6-NEXT: mtc1 $zero, $f0
282275
; MIPS64R6-NEXT: cmp.eq.s $f0, $f12, $f0
283276
; MIPS64R6-NEXT: mfc1 $1, $f0
284277
; MIPS64R6-NEXT: andi $1, $1, 1
285-
; MIPS64R6-NEXT: beqzc $1, .LBB1_2
286-
; MIPS64R6-NEXT: nop
278+
; MIPS64R6-NEXT: beqz $1, .LBB1_2
279+
; MIPS64R6-NEXT: sd $ra, 8($sp)
287280
; MIPS64R6-NEXT: # %bb.1: # %if.end
288281
; MIPS64R6-NEXT: jal f2
289282
; MIPS64R6-NEXT: nop

‎llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,11 @@
77

88
# ASM: # %bb.0:
99
# ASM-NEXT: daddiu $sp, $sp, -16
10-
# ASM-NEXT: sd $ra, 8($sp)
1110
## BUNDLE should be emitted in order:
1211
# ASM-NEXT: daddiu $sp, $sp, -16
1312
# ASM-NEXT: daddiu $sp, $sp, 16
1413
# ASM-NEXT: beqz $4, .LBB0_2
15-
# ASM-NEXT: nop
14+
# ASM-NEXT: sd $ra, 8($sp)
1615
--- |
1716
target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
1817
target triple = "mips64-unknown-freebsd"
@@ -87,15 +86,12 @@ body: |
8786
; CHECK: bb.0.entry:
8887
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
8988
; CHECK: $sp_64 = DADDiu $sp_64, -16
90-
; CHECK: CFI_INSTRUCTION def_cfa_offset 16
91-
; CHECK: SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
92-
; CHECK: CFI_INSTRUCTION offset $ra_64, -8
9389
; CHECK: BUNDLE {
9490
; CHECK: $sp_64 = DADDiu $sp_64, -16
9591
; CHECK: $sp_64 = DADDiu $sp_64, 16
9692
; CHECK: }
9793
; CHECK: BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at {
98-
; CHECK: $zero = SLL $zero, 0
94+
; CHECK: SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
9995
; CHECK: }
10096
; CHECK: bb.1.if.then:
10197
; CHECK: successors: %bb.3(0x80000000)
@@ -120,15 +116,14 @@ body: |
120116
liveins: $a0_64, $ra_64
121117
122118
$sp_64 = DADDiu $sp_64, -16
123-
CFI_INSTRUCTION def_cfa_offset 16
124-
SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
125-
CFI_INSTRUCTION offset $ra_64, -8
126119
; This BUNDLE instruction must not be split by the delay slot filler:
127120
BUNDLE {
128121
$sp_64 = DADDiu $sp_64, -16
129122
$sp_64 = DADDiu $sp_64, 16
130123
}
131-
BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at
124+
BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at {
125+
SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
126+
}
132127
133128
bb.1.if.then:
134129
successors: %bb.3(0x80000000)

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