Store UART clock divisor in UART module itself

Author: carlosedp

src/main/scala/MemoryIOManager.scala

@@ -62,11 +62,11 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
   io.Timer0Port.dataIn      := 0.U
   io.Timer0Port.writeEnable := false.B
 
-  val clockDivisor = RegInit(0.U(bitWidth.W))
-  io.UART0Port.clockDivisor  := clockDivisor
-  io.UART0Port.txQueue.valid := false.B
-  io.UART0Port.txQueue.bits  := 0.U
-  io.UART0Port.rxQueue.ready := false.B
+  io.UART0Port.txQueue.valid      := false.B
+  io.UART0Port.txQueue.bits       := 0.U
+  io.UART0Port.rxQueue.ready      := false.B
+  io.UART0Port.clockDivisor.bits  := 0.U
+  io.UART0Port.clockDivisor.valid := false.B
 
   io.DataMemPort.writeEnable  := false.B
   io.DataMemPort.writeData    := 0.U
@@ -117,10 +117,6 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
         .elsewhen(readAddress(7, 0) === 0x0c.U) {
           dataOut := Cat(io.UART0Port.txFull, io.UART0Port.rxFull, io.UART0Port.txEmpty, io.UART0Port.rxEmpty)
         }
-        /* Clock divisor */
-        .elsewhen(readAddress(7, 0) === 0x10.U) {
-          dataOut := clockDivisor
-        }
         /* Invalid */
         .otherwise(dataOut := 0.U)
     }
@@ -133,7 +129,8 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
       }
         /* clock divisor */
         .elsewhen(writeAddress(7, 0) === 0x10.U) {
-          clockDivisor := io.MemoryIOPort.writeData(7, 0)
+          io.UART0Port.clockDivisor.valid := true.B
+          io.UART0Port.clockDivisor.bits  := io.MemoryIOPort.writeData(7, 0)
         }
     }
   }

src/main/scala/Uart.scala

@@ -35,7 +35,7 @@ class UARTPort() extends Bundle {
   val txEmpty      = Output(Bool())
   val rxFull       = Output(Bool())
   val txFull       = Output(Bool())
-  val clockDivisor = Input(UInt(8.W))
+  val clockDivisor = Flipped(Valid(UInt(8.W)))
 }
 
 class Uart(val fifoLength: Int, val rxOverclock: Int) extends Module {
@@ -48,6 +48,11 @@ class Uart(val fifoLength: Int, val rxOverclock: Int) extends Module {
 
   val sampleClk        = RegInit(0.U(1.W))
   val sampleClkCounter = RegInit(0.U(8.W))
+  val clockDivisor     = RegInit(0.U(8.W))
+
+  when(io.dataPort.clockDivisor.valid) {
+    clockDivisor := io.dataPort.clockDivisor.bits
+  }
 
   val txQueue = Module(new Queue(UInt(8.W), fifoLength))
   val rxQueue = Module(new Queue(UInt(8.W), fifoLength))
@@ -57,10 +62,10 @@ class Uart(val fifoLength: Int, val rxOverclock: Int) extends Module {
   io.dataPort.rxFull  := (rxQueue.io.count === fifoLength.U)
   io.dataPort.txFull  := (txQueue.io.count === fifoLength.U)
 
-  val uartEnabled = io.dataPort.clockDivisor.orR
+  val uartEnabled = clockDivisor.orR
 
   when(uartEnabled) {
-    when(sampleClkCounter === io.dataPort.clockDivisor) {
+    when(sampleClkCounter === clockDivisor) {
       sampleClk        := 1.U
       sampleClkCounter := 0.U
     }.otherwise {

src/test/scala/UartSpec.scala

@@ -50,7 +50,8 @@ class UartSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matche
     test(new Uart(64, rxOverclock)).withAnnotations(Seq(WriteVcdAnnotation)) { u =>
       u.clock.setTimeout(10000)
 
-      u.io.dataPort.clockDivisor.poke(divider.U)
+      u.io.dataPort.clockDivisor.valid.poke(true.B)
+      u.io.dataPort.clockDivisor.bits.poke(divider.U)
 
       u.io.dataPort.rxQueue.ready.poke(false.B)
 

verilator/chiselv.cpp

@@ -79,7 +79,6 @@ int main(int argc, char **argv)
 // 		if (top->io_terminate)
 // 		{
 // 			VL_PRINTF("Simulation terminated!\n");
-			
 // 			VL_PRINTF("REG%d %x" VL_PRI64 "X\r\n", 0, top->Toplevel__DOT__CPU__DOT__registerBank__DOT__regs_0);
 // 			VL_PRINTF("REG%d %x" VL_PRI64 "X\r\n", 1, top->Toplevel__DOT__CPU__DOT__registerBank__DOT__regs_1);
 // 			VL_PRINTF("REG%d %x" VL_PRI64 "X\r\n", 2, top->Toplevel__DOT__CPU__DOT__registerBank__DOT__regs_2);