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carlosedpcarlosedp
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Bump scalafmt and re-lint with better rules
1 parent f73d654 commit 370b7ad

17 files changed

+45
-41
lines changed

‎.gitignore

+2-1
Original file line numberDiff line numberDiff line change
@@ -77,4 +77,5 @@ tmp
7777
/*.vcd
7878
/obj_dir
7979
/*.mem
80-
/chiselv
80+
/chiselv
81+
/tmphex/*

‎.scalafmt.conf

+2-2
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ danglingParentheses.callSite = true
1515
danglingParentheses.exclude = [
1616
"`trait`"
1717
]
18-
align.tokens.add = [
18+
align.tokens."+" = [
1919
{
2020
code = ":"
2121
}
@@ -24,7 +24,7 @@ optIn.annotationNewlines = true
2424
newlines.alwaysBeforeCurlyBraceLambdaParams = false
2525
newlines.alwaysBeforeMultilineDef = false
2626
newlines.implicitParamListModifierForce = [before]
27-
trailingCommas = "multiple"
27+
trailingCommas = "never"
2828

2929
rewrite.rules = [
3030
RedundantBraces,

‎build.sbt

+12-8
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ lazy val chiselv = (project in file("."))
2222
.settings(
2323
name := "chiselv",
2424
version := "1.0.0",
25-
scalaVersion := "2.13.6",
25+
scalaVersion := "2.13.6"
2626
)
2727

2828
// Default library versions
@@ -31,15 +31,18 @@ val defaultVersions = Map(
3131
"chiseltest" -> "0.5-SNAPSHOT",
3232
"scalatest" -> "3.2.10",
3333
"organize-imports" -> "0.5.0",
34-
"scalautils" -> "0.7.0",
34+
"scalautils" -> "0.8-SNAPSHOT"
3535
)
3636

3737
// Import libraries
38-
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % defaultVersions("chisel3")
39-
libraryDependencies += ("edu.berkeley.cs" %% "chiseltest" % defaultVersions("chiseltest") % "test").changing()
40-
41-
libraryDependencies += "org.scalatest" %% "scalatest" % defaultVersions("scalatest") % "test"
42-
libraryDependencies += "com.carlosedp" %% "scalautils" % defaultVersions("scalautils")
38+
libraryDependencies ++= Seq(
39+
"edu.berkeley.cs" %% "chisel3" % defaultVersions("chisel3"),
40+
("edu.berkeley.cs" %% "chiseltest" % defaultVersions("chiseltest") % "test").changing(),
41+
"org.scalatest" %% "scalatest" % defaultVersions("scalatest") % "test",
42+
"com.carlosedp" %% "scalautils" % defaultVersions("scalautils"),
43+
"com.lihaoyi" %% "os-lib" % "0.7.8",
44+
"edu.berkeley.cs" %% "firrtl" % "1.5-SNAPSHOT"
45+
)
4346
ThisBuild / scalafixDependencies += "com.github.liancheng" %% "organize-imports" % defaultVersions("organize-imports")
4447
addCompilerPlugin(("edu.berkeley.cs" % "chisel3-plugin" % defaultVersions("chisel3")).cross(CrossVersion.full))
4548

@@ -54,6 +57,7 @@ addCommandAlias("deps", "dependencyUpdates")
5457
resolvers ++= Seq(
5558
Resolver.sonatypeRepo("snapshots"),
5659
Resolver.sonatypeRepo("releases"),
60+
"Sonatype New OSS Snapshots" at "https://s01.oss.sonatype.org/content/repositories/snapshots"
5761
)
5862

5963
scalacOptions ++= Seq(
@@ -64,5 +68,5 @@ scalacOptions ++= Seq(
6468
"-Xcheckinit",
6569
"-Xfatal-warnings",
6670
"-Ywarn-dead-code",
67-
"-Ywarn-unused",
71+
"-Ywarn-unused"
6872
)

‎src/main/scala/ALU.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ class ALU(bitWidth: Int = 32) extends Module {
3535
(io.ALUPort.inst === ORI) -> OR,
3636
(io.ALUPort.inst === XORI) -> XOR,
3737
(io.ALUPort.inst === SLTI) -> SLT,
38-
(io.ALUPort.inst === SLTIU) -> SLTU,
39-
),
38+
(io.ALUPort.inst === SLTIU) -> SLTU
39+
)
4040
)
4141

4242
switch(op) {

‎src/main/scala/CPUSingleCycle.scala

+5-6
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ class CPUSingleCycle(
1111
bitWidth: Int = 32,
1212
instructionMemorySize: Int = 1 * 1024,
1313
dataMemorySize: Int = 1 * 1024,
14-
numGPIO: Int = 8,
14+
numGPIO: Int = 8
1515
) extends Module {
1616
val io = IO(new Bundle {
1717
val GPIO0External = Analog(numGPIO.W) // GPIO external port
@@ -69,7 +69,6 @@ class CPUSingleCycle(
6969
memoryIOManager.io.UART0Port <> io.UART0Port
7070

7171
// --------------- CPU Control --------------- //
72-
7372
// State of the CPU Stall
7473
stall := memoryIOManager.io.stall
7574
when(!stall) {
@@ -98,7 +97,7 @@ class CPUSingleCycle(
9897
ALU.io.ALUPort.b := Mux(
9998
decoder.io.DecoderPort.use_imm,
10099
decoder.io.DecoderPort.imm.asUInt,
101-
registerBank.io.regPort.rs2.asUInt,
100+
registerBank.io.regPort.rs2.asUInt
102101
)
103102

104103
registerBank.io.regPort.writeEnable := true.B
@@ -144,7 +143,7 @@ class CPUSingleCycle(
144143
// Set PC to jump address
145144
PC.io.pcPort.dataIn := Cat(
146145
(registerBank.io.regPort.rs1 + decoder.io.DecoderPort.imm).asUInt()(31, 1),
147-
0.U,
146+
0.U
148147
)
149148
}
150149
}
@@ -190,7 +189,7 @@ class CPUSingleCycle(
190189
dataSize := 2.U
191190
dataOut := Cat(
192191
Fill(16, memoryIOManager.io.MemoryIOPort.readData(15)),
193-
memoryIOManager.io.MemoryIOPort.readData(15, 0),
192+
memoryIOManager.io.MemoryIOPort.readData(15, 0)
194193
).asSInt
195194
}
196195
// Load Halfword Unsigned
@@ -203,7 +202,7 @@ class CPUSingleCycle(
203202
dataSize := 1.U
204203
dataOut := Cat(
205204
Fill(24, memoryIOManager.io.MemoryIOPort.readData(7)),
206-
memoryIOManager.io.MemoryIOPort.readData(7, 0),
205+
memoryIOManager.io.MemoryIOPort.readData(7, 0)
207206
).asSInt
208207
}
209208
// Load Byte Unsigned

‎src/main/scala/DataMemory.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ class DualPortRAM(
1818
bitWidth: Int = 32,
1919
sizeBytes: Long = 1,
2020
memoryFile: String = "",
21-
debugMsg: Boolean = false,
21+
debugMsg: Boolean = false
2222
) extends Module {
2323
val words = sizeBytes / bitWidth
2424
val io = IO(new Bundle() {

‎src/main/scala/GPIO.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,6 @@ class GPIOInOut(bitWidth: Int = 32, numGPIO: Int = 8) extends BlackBox(Map("WIDT
6969
| assign dataOut = dataIO;
7070
|
7171
|endmodule
72-
|""".stripMargin,
72+
|""".stripMargin
7373
)
7474
}

‎src/main/scala/InstructionMemory.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ class InstructionMemPort(val bitWidth: Int, val sizeBytes: Long) extends Bundle
1313
class InstructionMemory(
1414
bitWidth: Int = 32,
1515
sizeBytes: Long = 1,
16-
memoryFile: String = "",
16+
memoryFile: String = ""
1717
) extends Module {
1818
val words = sizeBytes / bitWidth
1919
val io = IO(new Bundle() {

‎src/main/scala/MemoryIOManager.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
8282
DACK := Mux(
8383
DACK > 0.U,
8484
DACK - 1.U,
85-
Mux((io.MemoryIOPort.readRequest || io.MemoryIOPort.writeRequest), stallLatency, 0.U),
85+
Mux((io.MemoryIOPort.readRequest || io.MemoryIOPort.writeRequest), stallLatency, 0.U)
8686
)
8787
io.stall := ((io.MemoryIOPort.readRequest || io.MemoryIOPort.writeRequest) && DACK =/= 1.U && stallEnable)
8888

@@ -256,7 +256,7 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
256256
Mux(writeMask(3), dataToWrite(3 * 8 + 7, 3 * 8), io.DataMemPort.readData(3 * 8 + 7, 3 * 8)),
257257
Mux(writeMask(2), dataToWrite(2 * 8 + 7, 2 * 8), io.DataMemPort.readData(2 * 8 + 7, 2 * 8)),
258258
Mux(writeMask(1), dataToWrite(1 * 8 + 7, 1 * 8), io.DataMemPort.readData(1 * 8 + 7, 1 * 8)),
259-
Mux(writeMask(0), dataToWrite(0 * 8 + 7, 0 * 8), io.DataMemPort.readData(0 * 8 + 7, 0 * 8)),
259+
Mux(writeMask(0), dataToWrite(0 * 8 + 7, 0 * 8), io.DataMemPort.readData(0 * 8 + 7, 0 * 8))
260260
)
261261
io.DataMemPort.writeData := dataIn
262262
dataOut := dataIn

‎src/main/scala/RVFI_Wrapper.scala

+3-3
Original file line numberDiff line numberDiff line change
@@ -33,13 +33,13 @@ class RVFICPUWrapper(
3333
bitWidth: Int = 32,
3434
instructionMemorySize: Int = 64 * 1024,
3535
dataMemorySize: Int = 64 * 1024,
36-
numGPIO: Int = 8,
36+
numGPIO: Int = 8
3737
) extends CPUSingleCycle(
3838
cpuFrequency,
3939
bitWidth,
4040
instructionMemorySize,
4141
dataMemorySize,
42-
numGPIO,
42+
numGPIO
4343
) {
4444
val rvfi = IO(new RVFIPort) // RVFI interface for RISCV-Formal
4545

@@ -80,7 +80,7 @@ class RVFICPUWrapper(
8080
rvfi.pc_wdata := Mux(
8181
PC.io.pcPort.writeAdd,
8282
(PC.io.pcPort.PC.asSInt + PC.io.pcPort.dataIn.asSInt).asUInt,
83-
PC.io.pcPort.PC4,
83+
PC.io.pcPort.PC4
8484
)
8585

8686
rvfi.mem_addr := Mux((decoder.io.DecoderPort.is_load || decoder.io.DecoderPort.is_store), ALU.io.ALUPort.x, 0.U)

‎src/main/scala/SOC.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ class SOC(
1010
dataMemorySize: Int = 1 * 1024,
1111
memoryFile: String = "",
1212
ramFile: String = "",
13-
numGPIO: Int = 8,
13+
numGPIO: Int = 8
1414
) extends Module {
1515
val io = IO(new Bundle {
1616
val led0 = Output(Bool()) // LED 0 is the heartbeat

‎src/main/scala/Toplevel.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class Toplevel(board: String, invReset: Boolean = true, cpuFrequency: Int) exten
3636
dataMemorySize = dataMemorySize,
3737
memoryFile = "progload.mem",
3838
ramFile = "progload-RAM.mem",
39-
numGPIO = numGPIO,
39+
numGPIO = numGPIO
4040
)
4141
)
4242

@@ -65,6 +65,6 @@ object Toplevel extends App {
6565
// Generate Verilog
6666
(new chisel3.stage.ChiselStage).emitVerilog(
6767
new Toplevel(board, invReset, cpuFrequency),
68-
chiselargs,
68+
chiselargs
6969
)
7070
}

‎src/test/scala/CPUSingleCycleAppsSpec.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ class CPUSingleCycleWrapperApps(
1313
bitWidth: Int,
1414
instructionMemorySize: Int,
1515
memorySize: Int,
16-
memoryFile: String,
16+
memoryFile: String
1717
) extends SOC(cpuFrequency, bitWidth, instructionMemorySize, memorySize, memoryFile) {
1818
val registers = expose(core.registerBank.regs)
1919
val memWriteAddr = expose(core.memoryIOManager.io.MemoryIOPort.writeAddr)
@@ -37,7 +37,7 @@ class CPUSingleCycleAppsSpec extends AnyFlatSpec with ChiselScalatestTester with
3737
.withAnnotations(
3838
Seq(
3939
WriteVcdAnnotation,
40-
VerilatorBackendAnnotation,
40+
VerilatorBackendAnnotation
4141
)
4242
)
4343

‎src/test/scala/DecoderSpec.scala

+3-3
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with should.Mat
7878
rs2: Int,
7979
imm: Int,
8080
toALU: Bool,
81-
branch: Bool,
81+
branch: Bool
8282
) = {
8383
c.io.DecoderPort.inst.expect(inst)
8484
c.io.DecoderPort.rd.peek().litValue should be(rd)
@@ -96,14 +96,14 @@ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with should.Mat
9696
"b0000000%05d%05d000%05d0110011",
9797
rs2.toBinaryString.toInt,
9898
rs1.toBinaryString.toInt,
99-
rd.toBinaryString.toInt,
99+
rd.toBinaryString.toInt
100100
)
101101
case ANDI =>
102102
String.format(
103103
"b%12s%05d111%05d0010011",
104104
imm.toBinaryString.takeRight(12),
105105
rs1.toBinaryString.toInt,
106-
rd.toBinaryString.toInt,
106+
rd.toBinaryString.toInt
107107
)
108108
}
109109
}

‎src/test/scala/GPIOSpec.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ class GPIOSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matche
1919
test(new GPIOWrapper(32, 8)).withAnnotations(
2020
Seq(
2121
WriteVcdAnnotation,
22-
VerilatorBackendAnnotation,
22+
VerilatorBackendAnnotation
2323
)
2424
)
2525

‎src/test/scala/MemoryIOManagerSpec.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ class MemoryIOManagerSpec extends AnyFlatSpec with ChiselScalatestTester with sh
1414
test(new MemoryIOManager(32, 50000000, 1024)).withAnnotations(
1515
Seq(
1616
WriteVcdAnnotation,
17-
VerilatorBackendAnnotation,
17+
VerilatorBackendAnnotation
1818
)
1919
)
2020

‎src/test/scala/SOCDemoAppsSpec.scala

+4-4
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ class SOCWrapperDemo(
1515
memorySize: Int,
1616
memoryFile: String,
1717
ramFile: String,
18-
numGPIO: Int,
18+
numGPIO: Int
1919
// baudRate: Int,
2020
) extends SOC(
2121
cpuFrequency,
@@ -24,7 +24,7 @@ class SOCWrapperDemo(
2424
memorySize,
2525
memoryFile,
2626
ramFile,
27-
numGPIO,
27+
numGPIO
2828
) {
2929
val registers = expose(core.registerBank.regs)
3030
val pc = expose(core.PC.pc)
@@ -47,14 +47,14 @@ class CPUDemoAppsSpec extends AnyFlatSpec with ChiselScalatestTester with should
4747
memorySize,
4848
memoryfile,
4949
ramFile,
50-
8,
50+
8
5151
// 1200,
5252
)
5353
)
5454
.withAnnotations(
5555
Seq(
5656
WriteVcdAnnotation,
57-
VerilatorBackendAnnotation,
57+
VerilatorBackendAnnotation
5858
)
5959
)
6060

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