Add Digilent ArtyA7-35T FPGA board via open-source Symbiflow

Author: carlosedp

constraints/arty_a7.xdc

@@ -1,18 +1,31 @@
 # Clock pin
-set_property PACKAGE_PIN E3 [get_ports {clock}]
-set_property IOSTANDARD LVCMOS33 [get_ports {clock}]
+set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {clock}]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {clock}]
+
+# Reset
+set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { reset }]
 
 # LEDs
-set_property PACKAGE_PIN H5  [get_ports {io_led0}]
-set_property PACKAGE_PIN J5  [get_ports {io_GPIO0[0]}]
-set_property PACKAGE_PIN T9  [get_ports {io_GPIO0[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {io_led0}]
-set_property IOSTANDARD LVCMOS33 [get_ports {io_GPIO0}]
-set_property IOSTANDARD LVCMOS33 [get_ports {io_GPIO0[1]}]
+set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports {io_led0}]
+set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports {io_GPIO0[0]}]
+set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports {io_GPIO0[1]}]
+set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports {io_GPIO0[2]}]
+
+set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { io_GPIO0[3] }]; #IO_L24P_T3_35 Sch=led3_g
+set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { io_GPIO0[4] }]; #IO_L22N_T3_35 Sch=led2_g
+set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { io_GPIO0[5] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
+set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { io_GPIO0[6] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
+
+##Buttons
+set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { io_GPIO0[7] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+# set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { io_GPIO0[8] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
+# set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
+# set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
+
+##USB-UART Interface
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { io_UART0tx }];
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { io_UART0rx }];
 
-# Switches
-set_property PACKAGE_PIN D9 [get_ports { reset }]
-set_property IOSTANDARD LVCMOS33 [get_ports { reset }]
 
-# Clock constraints
-create_clock -period 10.0 [get_ports {clock}]

openocd/digilent-hs1.cfg

@@ -1,7 +1,7 @@
 # this supports JTAG-HS1 and JTAG-SMT1
 # (the later being the OEM on-board version)
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Digilent USB Device"
 ftdi_vid_pid 0x0403 0x6010
 # channel 1 does not have any functionality
@@ -11,4 +11,4 @@ ftdi_layout_init 0x0088 0x008b
 reset_config none
 
 # default speed
-adapter_khz 5000
+adapter speed 5000

openocd/ecp5-evn.cfg

@@ -1,6 +1,6 @@
 # this supports ECP5 Evaluation Board
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Lattice ECP5 Evaluation Board"
 ftdi_vid_pid 0x0403 0x6010
 # channel 1 does not have any functionality
@@ -10,4 +10,4 @@ ftdi_layout_init 0xfff8 0xfffb
 reset_config none
 
 # default speed
-adapter_khz 5000
+adapter speed 5000

src/main/resources/pll_artya7-35t.v

@@ -1,17 +1,85 @@
+
+// file: chiselv_pll0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// ____clko__15.00000______0.000______50.0______387.320____261.747
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
 `timescale 1ps/1ps
 
 module PLL0
 
- (
+ (// Clock in ports
+  // Clock out ports
   output        clko,
+  // Status and control signals
   output        lock,
   input         clki
  );
   // Input buffering
   //------------------------------------
-wire clki_clk_wiz_0;
+wire clki_chiselv_pll0;
+wire clk_in2_chiselv_pll0;
   IBUF clkin1_ibufg
-   (.O (clki_clk_wiz_0),
+   (.O (clki_chiselv_pll0),
     .I (clki));
 
   // Clocking PRIMITIVE
@@ -21,20 +89,20 @@ wire clki_clk_wiz_0;
   //    * Unused inputs are tied off
   //    * Unused outputs are labeled unused
 
-  wire        clko_clk_wiz_0;
-  wire        clk_out2_clk_wiz_0;
-  wire        clk_out3_clk_wiz_0;
-  wire        clk_out4_clk_wiz_0;
-  wire        clk_out5_clk_wiz_0;
-  wire        clk_out6_clk_wiz_0;
-  wire        clk_out7_clk_wiz_0;
+  wire        clko_chiselv_pll0;
+  wire        clk_out2_chiselv_pll0;
+  wire        clk_out3_chiselv_pll0;
+  wire        clk_out4_chiselv_pll0;
+  wire        clk_out5_chiselv_pll0;
+  wire        clk_out6_chiselv_pll0;
+  wire        clk_out7_chiselv_pll0;
 
   wire [15:0] do_unused;
   wire        drdy_unused;
   wire        psdone_unused;
   wire        lock_int;
-  wire        clkfbout_clk_wiz_0;
-  wire        clkfbout_buf_clk_wiz_0;
+  wire        clkfbout_chiselv_pll0;
+  wire        clkfbout_buf_chiselv_pll0;
   wire        clkfboutb_unused;
    wire clkout1_unused;
    wire clkout2_unused;
@@ -52,25 +120,25 @@ wire clki_clk_wiz_0;
     .DIVCLK_DIVIDE        (4),
     .CLKFBOUT_MULT        (33),
     .CLKFBOUT_PHASE       (0.000),
-    .CLKOUT0_DIVIDE       (33),
+    .CLKOUT0_DIVIDE       (55),
     .CLKOUT0_PHASE        (0.000),
     .CLKOUT0_DUTY_CYCLE   (0.500),
-    .CLKIN1_PERIOD        (10.000),
-    .CLKIN2_PERIOD        (10.312))
+    .CLKIN1_PERIOD        (10.000))
   plle2_adv_inst
     // Output clocks
    (
-    .CLKFBOUT            (clkfbout_clk_wiz_0),
-    .CLKOUT0             (clko_clk_wiz_0),
+    .CLKFBOUT            (clkfbout_chiselv_pll0),
+    .CLKOUT0             (clko_chiselv_pll0),
     .CLKOUT1             (clkout1_unused),
     .CLKOUT2             (clkout2_unused),
     .CLKOUT3             (clkout3_unused),
     .CLKOUT4             (clkout4_unused),
     .CLKOUT5             (clkout5_unused),
      // Input clock control
-    .CLKFBIN             (clkfbout_buf_clk_wiz_0),
-    .CLKIN1              (clki_clk_wiz_0),
-    .CLKIN2              (clki_clk_wiz_0),
+    .CLKFBIN             (clkfbout_buf_chiselv_pll0),
+    .CLKIN1              (clki_chiselv_pll0),
+    .CLKIN2              (1'b0),
+     // Tied to always select the primary input clock
     .CLKINSEL            (1'b1),
     // Ports for dynamic reconfiguration
     .DADDR               (7'h0),
@@ -92,11 +160,12 @@ wire clki_clk_wiz_0;
   //-----------------------------------
 
   BUFG clkf_buf
-   (.O (clkfbout_buf_clk_wiz_0),
-    .I (clkfbout_clk_wiz_0));
+   (.O (clkfbout_buf_chiselv_pll0),
+    .I (clkfbout_chiselv_pll0));
 
   BUFG clkout1_buf
    (.O   (clko),
-    .I   (clko_clk_wiz_0));
+    .I   (clko_chiselv_pll0));
+
 
 endmodule