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Copy file name to clipboardExpand all lines: README.md
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## Generating Verilog
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Verilog code can be generated from Chisel by using the `chisel` Makefile target. It requires a `-board` parameter so the correct PLL is included in the design. If it's not provided, a bypass PLL will be used.
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Verilog code can be generated from Chisel sources by using the `chisel` Makefile target. If a `-board` parameter is passed, the target board PLL is included in the design. If it's not provided, a bypass PLL will be used.
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```sh
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make chisel BOARD=artya7-35
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```
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The `BOARD` argument must match one of the `pll_BOARD.v]` files in `/src/main/resources` directory.
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The `BOARD` argument must match one of the `pll_BOARD.v` files in `/src/main/resources` directory.
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The core can be simulated in Verilator using the commands:
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```sh
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make verilator # this will build the SOC, generate the Verilog files and Verilator project
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make verirun # This will copy the UART demo (RAM/ROM) from gcc/helloUART and run Verilator
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make verirun # This will copy the UART demo (RAM/ROM) binaries from gcc/helloUART and run Verilator
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```
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The demo application can be adjusted in the Makefile to point to the dir and files for ROM and RAM.
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## Building for FPGAs
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The standard build process uses locally installed tools like Java (for Chisel generation), Yosys, NextPNR, Vivado and others. It's recommended to use [Fusesoc](https://github.com/olofk/fusesoc) for building the complete workflow by using containers thru a command launcher.
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The standard build process uses locally installed tools like Java (for Chisel generation), Yosys, NextPNR, Vivado and others. It's recommended to use [Fusesoc](https://github.com/olofk/fusesoc) for building the complete workflow by using containers thru a command launcher. In this case, the FPGA tools doesn't need to be installed locally.
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