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Update libraries, improve buildfiles
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5 files changed

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Makefile

+11-11
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
# Source and target files/directories
2-
project = $(shell grep object build.sc |grep -v extends |sed s/object//g |xargs)
32
scala_files = $(wildcard src/main/scala/*.scala)
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generated_files = generated
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BUILDTOOL ?= sbt # Can also be mill
@@ -16,9 +15,10 @@ else
1615
endif
1716

1817
# Define utility applications
19-
# VERILATOR= docker $(DOCKERARGS) hdlc/verilator verilator # Docker Verilator
20-
VERILATOR=verilator # Local Verilator
2118
YOSYS = docker $(DOCKERARGS) hdlc/yosys yosys
19+
VERILATORARGS = --name verilator --hostname verilator --rm -it --entrypoint= -v $(PWD):/work -w /work
20+
VERILATOR= # Local Verilator
21+
# VERILATOR = docker $(DOCKERARGS) $(VERILATORARGS) verilator/verilator
2222

2323
# Default board PLL
2424
BOARD := bypass
@@ -35,13 +35,15 @@ $(generated_files): $(scala_files) build.sbt
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@if [ $(BUILDTOOL) = "sbt" ]; then \
3636
${SBT} "run $(CHISELPARAMS) $(BOARDPARAMS)"; \
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elif [ $(BUILDTOOL) = "mill" ]; then \
38+
project=grep object build.sc |grep -v extends |sed s/object//g |xargs \
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scripts/mill $(project).run $(CHISELPARAMS) $(BOARDPARAMS); \
3940
fi
4041

4142
chisel_tests:
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@if [ $(BUILDTOOL) = "sbt" ]; then \
4344
${SBT} "test"; \
4445
elif [ $(BUILDTOOL) = "mill" ]; then \
46+
project=grep object build.sc |grep -v extends |sed s/object//g |xargs \
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scripts/mill $(project).test; \
4648
fi
4749

@@ -52,21 +54,19 @@ check: chisel_tests ## Run Chisel tests
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test: chisel_tests
5355

5456
# This section defines the Verilator simulation and demo application to be used
55-
# Adjust the rom and ram files below to match your test
56-
romfile = gcc/helloUART/main-rom.mem
57-
ramfile = gcc/helloUART/main-ram.mem
5857
verilator: $(generated_files) ## Generate Verilator simulation
5958
@rm -rf obj_dir
60-
$(VERILATOR) -O3 --assert $(foreach f,$(wildcard generated/*.v),--cc $(f)) --exe verilator/chiselv.cpp verilator/uart.c --top-module Toplevel -o chiselv --timescale 1ns/1ps
61-
@make -C obj_dir -f VToplevel.mk -j`nproc`
59+
$(VERILATOR) verilator -O3 --assert $(foreach f,$(wildcard generated/*.v),--cc $(f)) --exe verilator/chiselv.cpp verilator/uart.c --top-module Toplevel -o chiselv --timescale 1ns/1ps
60+
make -C obj_dir -f VToplevel.mk -j`nproc`
6261
@cp obj_dir/chiselv .
63-
@cp $(romfile) progload.mem
64-
@cp $(ramfile) progload-RAM.mem
6562

63+
# Adjust the rom and ram files below to match your test
64+
romfile = gcc/helloUART/main-rom.mem
65+
ramfile = gcc/helloUART/main-ram.mem
6666
verirun: ## Run Verilator simulation with ROM and RAM files to be loaded
6767
@cp $(romfile) progload.mem
6868
@cp $(ramfile) progload-RAM.mem
69-
./chiselv
69+
@bash -c "trap 'reset' EXIT; ./chiselv"
7070

7171
MODULE ?= Toplevel
7272
dot: $(generated_files) ## Generate dot files for Core

README.md

+4-4
Original file line numberDiff line numberDiff line change
@@ -34,26 +34,26 @@ Currently the target builds a RV32I core.
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3535
## Generating Verilog
3636

37-
Verilog code can be generated from Chisel by using the `chisel` Makefile target. It requires a `-board` parameter so the correct PLL is included in the design. If it's not provided, a bypass PLL will be used.
37+
Verilog code can be generated from Chisel sources by using the `chisel` Makefile target. If a `-board` parameter is passed, the target board PLL is included in the design. If it's not provided, a bypass PLL will be used.
3838

3939
```sh
4040
make chisel BOARD=artya7-35
4141
```
4242

43-
The `BOARD` argument must match one of the `pll_BOARD.v]` files in `/src/main/resources` directory.
43+
The `BOARD` argument must match one of the `pll_BOARD.v` files in `/src/main/resources` directory.
4444

4545
The core can be simulated in Verilator using the commands:
4646

4747
```sh
4848
make verilator # this will build the SOC, generate the Verilog files and Verilator project
49-
make verirun # This will copy the UART demo (RAM/ROM) from gcc/helloUART and run Verilator
49+
make verirun # This will copy the UART demo (RAM/ROM) binaries from gcc/helloUART and run Verilator
5050
```
5151

5252
The demo application can be adjusted in the Makefile to point to the dir and files for ROM and RAM.
5353

5454
## Building for FPGAs
5555

56-
The standard build process uses locally installed tools like Java (for Chisel generation), Yosys, NextPNR, Vivado and others. It's recommended to use [Fusesoc](https://github.com/olofk/fusesoc) for building the complete workflow by using containers thru a command launcher.
56+
The standard build process uses locally installed tools like Java (for Chisel generation), Yosys, NextPNR, Vivado and others. It's recommended to use [Fusesoc](https://github.com/olofk/fusesoc) for building the complete workflow by using containers thru a command launcher. In this case, the FPGA tools doesn't need to be installed locally.
5757

5858
### Fusesoc build and generation
5959

build.sbt

+21-18
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,17 @@
33
ThisBuild / organization := "com.carlosedp"
44
ThisBuild / description := "ChiselV is a RISC-V core written in Chisel"
55
ThisBuild / homepage := Some(url("https://carlosedp.com"))
6-
ThisBuild / licenses := Seq("MIT" -> url("https://opensource.org/licenses/MIT"))
6+
ThisBuild / licenses := Seq("BSD 3-Clause" -> url("https://github.com/carlosedp/chiselv/blob/main/LICENSE"))
77
ThisBuild / scmInfo := Some(
88
ScmInfo(url("https://github.com/carlosedp/chiselv"), "[email protected]:carlosedp/chiselv.git")
99
)
1010
ThisBuild / developers := List(
1111
Developer("carlosedp", "Carlos Eduardo de Paula", "[email protected]", url("https://github.com/carlosedp"))
1212
)
13+
1314
ThisBuild / scalafixDependencies += "com.github.liancheng" %% "organize-imports" % "0.5.0"
1415
Global / semanticdbEnabled := true
15-
Global / semanticdbVersion := "4.4.28" //scalafixSemanticdb.revision // Force version due to compatibility issues
16+
Global / semanticdbVersion := scalafixSemanticdb.revision
1617
Global / onChangedBuildSource := ReloadOnSourceChanges
1718

1819
Compile / run / mainClass := Some("chiselv.Toplevel")
@@ -22,29 +23,31 @@ lazy val chiselv = (project in file("."))
2223
.settings(
2324
name := "chiselv",
2425
version := "1.0.0",
25-
scalaVersion := "2.13.6"
26+
scalaVersion := "2.13.7"
2627
)
2728

2829
// Default library versions
29-
val defaultVersions = Map(
30-
"chisel3" -> "3.5.0-RC1",
31-
"chiseltest" -> "0.5-SNAPSHOT",
32-
"scalatest" -> "3.2.10",
33-
"organize-imports" -> "0.5.0",
34-
"scalautils" -> "0.7.2"
35-
)
30+
lazy val versions = new {
31+
val chisel3 = "3.5.0-RC2"
32+
// val firrtl = "1.5-SNAPSHOT"
33+
val chiseltest = "0.5.0-RC2"
34+
val scalatest = "3.2.10"
35+
val organizeimports = "0.5.0"
36+
val scalautils = "0.7.2"
37+
val oslib = "0.8.0"
38+
}
3639

3740
// Import libraries
3841
libraryDependencies ++= Seq(
39-
"edu.berkeley.cs" %% "chisel3" % defaultVersions("chisel3"),
40-
"edu.berkeley.cs" %% "chiseltest" % defaultVersions("chiseltest") % "test",
41-
"org.scalatest" %% "scalatest" % defaultVersions("scalatest") % "test",
42-
"com.carlosedp" %% "scalautils" % defaultVersions("scalautils"),
43-
"com.lihaoyi" %% "os-lib" % "0.7.8",
44-
"edu.berkeley.cs" %% "firrtl" % "1.5-SNAPSHOT" // Force using SNAPSHOT until next RC is cut (memory synth)
42+
"edu.berkeley.cs" %% "chisel3" % versions.chisel3,
43+
"edu.berkeley.cs" %% "chiseltest" % versions.chiseltest % "test",
44+
"org.scalatest" %% "scalatest" % versions.scalatest % "test",
45+
"com.carlosedp" %% "scalautils" % versions.scalautils,
46+
"com.lihaoyi" %% "os-lib" % versions.oslib
47+
// "edu.berkeley.cs" %% "firrtl" % versions.firrtl // Force using SNAPSHOT until next RC is cut (memory synth)
4548
)
46-
ThisBuild / scalafixDependencies += "com.github.liancheng" %% "organize-imports" % defaultVersions("organize-imports")
47-
addCompilerPlugin(("edu.berkeley.cs" % "chisel3-plugin" % defaultVersions("chisel3")).cross(CrossVersion.full))
49+
ThisBuild / scalafixDependencies += "com.github.liancheng" %% "organize-imports" % versions.organizeimports
50+
addCompilerPlugin(("edu.berkeley.cs" % "chisel3-plugin" % versions.chisel3).cross(CrossVersion.full))
4851

4952
// Aliases
5053
addCommandAlias("com", "all compile test:compile")

project/build.properties

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
sbt.version=1.5.5
1+
sbt.version=1.6.1

project/plugins.sbt

+3-3
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@@ -1,3 +1,3 @@
1-
addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.4")
2-
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.32")
3-
addSbtPlugin("com.timushev.sbt" % "sbt-updates" % "0.6.0")
1+
addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.6")
2+
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.33")
3+
addSbtPlugin("com.timushev.sbt" % "sbt-updates" % "0.6.1")

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